6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-17 21:29:20 +00:00
Code Issues Projects Releases Wiki Activity

Allow the target to override the ISD::CondCode that's to be used to test the

Browse Source 
result of the comparison libcall against zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-01-31 09:29:11 +00:00
parent 991d3616c8
commit d385fd62cb
3 changed files with 45 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
include/llvm/Target/TargetLowering.h
View File

@ -855,6 +855,18 @@ public:
return LibcallRoutineNames[Call];
}
/// setCmpLibcallCC - Override the default CondCode to be used to test the
/// result of the comparison libcall against zero.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
CmpLibcallCCs[Call] = CC;
}
/// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
/// the comparison libcall against zero.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
return CmpLibcallCCs[Call];
}
protected:
/// addLegalAddressScale - Add a integer (> 1) value which can be used as
/// scale in the target addressing mode. Note: the ordering matters so the
@ -992,6 +1004,10 @@ private:
///
const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
/// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
/// of each of the comparison libcall against zero.
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
protected:
/// When lowering %llvm.memset this field specifies the maximum number of
/// store operations that may be substituted for the call to memset. Targets

22
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -3604,72 +3604,58 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
switch (cast<CondCodeSDNode>(CC)->get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
CC1 = ISD::SETEQ;
break;
case ISD::SETNE:
case ISD::SETUNE:
LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
CC1 = ISD::SETNE;
break;
case ISD::SETGE:
case ISD::SETOGE:
LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
CC1 = ISD::SETGE;
break;
case ISD::SETLT:
case ISD::SETOLT:
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
CC1 = ISD::SETLT;
break;
case ISD::SETLE:
case ISD::SETOLE:
LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
CC1 = ISD::SETLE;
break;
case ISD::SETGT:
case ISD::SETOGT:
LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
CC1 = ISD::SETGT;
break;
case ISD::SETUO:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
break;
case ISD::SETO:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
CC1 = cast<CondCodeSDNode>(CC)->get() == ISD::SETO
? ISD::SETEQ : ISD::SETNE;
break;
default:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
CC1 = ISD::SETNE;
switch (cast<CondCodeSDNode>(CC)->get()) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
CC1 = ISD::SETLT;
// Fallthrough
case ISD::SETUGT:
LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
CC2 = ISD::SETGT;
break;
case ISD::SETUGE:
LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
CC2 = ISD::SETGE;
break;
case ISD::SETULT:
LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
CC2 = ISD::SETLT;
break;
case ISD::SETULE:
LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
CC2 = ISD::SETLE;
break;
case ISD::SETUEQ:
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
CC2 = ISD::SETEQ;
break;
default: assert(0 && "Unsupported FP setcc!");
}
@ -3680,14 +3666,14 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(CC1);
CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
LHS = ExpandLibCall(TLI.getLibcallName(LC2),
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
DAG.getCondCode(CC2));
DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDOperand();
}

25
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -94,6 +94,30 @@ static void InitLibcallNames(const char **Names) {
Names[RTLIB::OGT_F64] = "__gtdf2";
Names[RTLIB::UO_F32] = "__unordsf2";
Names[RTLIB::UO_F64] = "__unorddf2";
Names[RTLIB::O_F32] = "__unordsf2";
Names[RTLIB::O_F64] = "__unorddf2";
}
/// InitCmpLibcallCCs - Set default comparison libcall CC.
///
static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
CCs[RTLIB::UNE_F32] = ISD::SETNE;
CCs[RTLIB::UNE_F64] = ISD::SETNE;
CCs[RTLIB::OGE_F32] = ISD::SETGE;
CCs[RTLIB::OGE_F64] = ISD::SETGE;
CCs[RTLIB::OLT_F32] = ISD::SETLT;
CCs[RTLIB::OLT_F64] = ISD::SETLT;
CCs[RTLIB::OLE_F32] = ISD::SETLE;
CCs[RTLIB::OLE_F64] = ISD::SETLE;
CCs[RTLIB::OGT_F32] = ISD::SETGT;
CCs[RTLIB::OGT_F64] = ISD::SETGT;
CCs[RTLIB::UO_F32] = ISD::SETNE;
CCs[RTLIB::UO_F64] = ISD::SETNE;
CCs[RTLIB::O_F32] = ISD::SETEQ;
CCs[RTLIB::O_F64] = ISD::SETEQ;
}
TargetLowering::TargetLowering(TargetMachine &tm)
@ -132,6 +156,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
JumpBufAlignment = 0;
InitLibcallNames(LibcallRoutineNames);
InitCmpLibcallCCs(CmpLibcallCCs);
}
TargetLowering::~TargetLowering() {}