6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-22 10:29:35 +00:00
Code Issues Projects Releases Wiki Activity

Fixes an assertion failure while disassembling ARM rsbs reg/reg form.

Browse Source 
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2011-03-02 23:08:33 +00:00
parent 4670353a21
commit d39647d913
2 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2203,6 +2203,19 @@ def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
}
def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -130,3 +130,6 @@
# CHECK: msr cpsr_fc, r0
0x00 0xf0 0x29 0xe1
# CHECK: rsbs r6, r7, r8
0x08 0x60 0x77 0xe0