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https://github.com/c64scene-ar/llvm-6502.git
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Reorganize logical and arithmetic SSE 1 & 2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106557 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
f23919b3e9
commit
d3a067bbc2
@ -834,6 +834,10 @@ def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Logical Instructions
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//===----------------------------------------------------------------------===//
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/// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
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///
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multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
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@ -868,6 +872,82 @@ defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
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let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
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/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
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///
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode, int HasPat = 0,
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list<list<dag>> Pattern = []> {
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let isAsmParserOnly = 1 in {
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defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>, TB;
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defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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TB, OpSize;
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}
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}
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defm AND : sse12_fp_packed_logical<0x54, "and", and>;
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defm OR : sse12_fp_packed_logical<0x56, "or", or>;
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defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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let isCommutable = 0 in
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
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// single r+r
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[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
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(bc_v2i64 (v4i32 immAllOnesV))),
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VR128:$src2)))],
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// double r+r
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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(bc_v2i64 (v2f64 VR128:$src2))))],
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// single r+m
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[(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
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(bc_v2i64 (v4i32 immAllOnesV))),
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(memopv2i64 addr:$src2))))],
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// double r+m
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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(memopv2i64 addr:$src2)))]]>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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/// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
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/// vector forms.
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///
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@ -876,8 +956,7 @@ let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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/// plain scalar form, in that it takes an entire vector (instead of a scalar)
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/// and leaves the top elements unmodified (therefore these cannot be commuted).
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///
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/// These three forms can each be reg+reg or reg+mem, so there are a total of
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/// six "instructions".
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/// These three forms can each be reg+reg or reg+mem.
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///
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multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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@ -953,8 +1032,6 @@ let isCommutable = 0 in {
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/// onto C operators don't use this form since they just use the plain
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/// vector form instead of having a separate vector intrinsic form.
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///
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/// This provides a total of eight "instructions".
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///
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multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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@ -1210,79 +1287,6 @@ defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
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defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
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int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
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/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
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///
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multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode, int HasPat = 0,
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list<list<dag>> Pattern = []> {
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let isAsmParserOnly = 1 in {
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defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>, TB;
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defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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TB, OpSize;
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}
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}
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// Logical
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defm AND : sse12_fp_packed_logical<0x54, "and", and>;
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defm OR : sse12_fp_packed_logical<0x56, "or", or>;
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defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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let isCommutable = 0 in
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
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// single r+r
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[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
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(bc_v2i64 (v4i32 immAllOnesV))),
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VR128:$src2)))],
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// double r+r
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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(bc_v2i64 (v2f64 VR128:$src2))))],
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// single r+m
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[(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
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(bc_v2i64 (v4i32 immAllOnesV))),
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(memopv2i64 addr:$src2))))],
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// double r+m
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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(memopv2i64 addr:$src2)))]]>;
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let Constraints = "$src1 = $dst" in {
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def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
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