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Added new features to represent specific instructions groups

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2008-07-30 17:01:06 +00:00
parent f7d66f7345
commit d3a680dda5
3 changed files with 45 additions and 8 deletions
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16
lib/Target/Mips/Mips.td
View File

@ -49,6 +49,16 @@ def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
"true", "Enable vector FPU instructions.">;
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
"Enable 'signext in register' instructions.">;
def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
"Enable 'conditional move' instructions.">;
def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
"Enable 'multiply add/sub' instructions.">;
def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true",
"Enable 'min/max' instructions.">;
def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
"Enable 'byte/half swap' instructions.">;
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
"Enable 'count leading bits' instructions.">;
//===----------------------------------------------------------------------===//
// Mips processors supported.
@ -65,9 +75,11 @@ def : Proc<"mips2", [FeatureMips2]>;
def : Proc<"r6000", [FeatureMips2]>;
// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
// but much more similar to Mips2 than Mips3.
// but much more similar to Mips2 than Mips3. It also contains some of
// Mips32/Mips32r2 instructions and a custom vector fpu processor.
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
FeatureSEInReg, FeatureVFPU]>;
FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
FeatureMinMax, FeatureSwap, FeatureBitCount]>;
def Mips : Target {
let InstructionSet = MipsInstrInfo;

5
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -29,8 +29,9 @@ cl::opt<unsigned> SSThreshold("mips-ssection-threshold", cl::Hidden,
MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
const std::string &FS, bool little) :
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false),
HasABICall(true), HasAbsoluteCall(false), IsLinux(true)
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasABICall(true),
HasAbsoluteCall(false), IsLinux(true), HasSEInReg(false), HasCondMov(false),
HasMulDivAdd(false), HasMinMax(false), HasSwap(false), HasBitCount(false)
{
std::string CPU = "mips1";

32
lib/Target/Mips/MipsSubtarget.h
View File

@ -58,9 +58,6 @@ protected:
// HasVFPU - Processor has a vector floating point unit.
bool HasVFPU;
// HasSEInReg - Target has SEB and SEH (signext in register) instructions.
bool HasSEInReg;
// IsABICall - Enable SRV4 code for SVR4-style dynamic objects
bool HasABICall;
@ -75,6 +72,27 @@ protected:
// bytes into the small data or bss section. The default is 8.
unsigned SSectionThreshold;
/// Features related to the presence of specific instructions.
// HasSEInReg - SEB and SEH (signext in register) instructions.
bool HasSEInReg;
// HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
bool HasCondMov;
// HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
// instructions.
bool HasMulDivAdd;
// HasMinMax - MIN and MAX instructions.
bool HasMinMax;
// HasSwap - Byte and half swap instructions.
bool HasSwap;
// HasBitCount - Count leading '1' and '0' bits.
bool HasBitCount;
InstrItineraryData InstrItins;
public:
@ -102,12 +120,18 @@ public:
bool isSingleFloat() const { return IsSingleFloat; };
bool isNotSingleFloat() const { return !IsSingleFloat; };
bool hasVFPU() const { return HasVFPU; };
bool hasSEInReg() const { return HasSEInReg; };
bool hasABICall() const { return HasABICall; };
bool hasAbsoluteCall() const { return HasAbsoluteCall; };
bool isLinux() const { return IsLinux; };
unsigned getSSectionThreshold() const { return SSectionThreshold; }
/// Features related to the presence of specific instructions.
bool hasSEInReg() const { return HasSEInReg; };
bool hasCondMov() const { return HasCondMov; };
bool hasMulDivAdd() const { return HasMulDivAdd; };
bool hasMinMax() const { return HasMinMax; };
bool hasSwap() const { return HasSwap; };
bool hasBitCount() const { return HasBitCount; };
};
} // End llvm namespace