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Remove references to INSERT_SUBREG after de-SSA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107732 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -54,7 +54,6 @@ namespace {
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private:
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bool LowerExtract(MachineInstr *MI);
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bool LowerInsert(MachineInstr *MI);
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bool LowerSubregToReg(MachineInstr *MI);
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bool LowerCopy(MachineInstr *MI);
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@@ -238,90 +237,6 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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return true;
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}
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bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
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(MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
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(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
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MI->getOperand(3).isImm() && "Invalid insert_subreg");
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unsigned DstReg = MI->getOperand(0).getReg();
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#ifndef NDEBUG
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unsigned SrcReg = MI->getOperand(1).getReg();
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#endif
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unsigned InsReg = MI->getOperand(2).getReg();
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unsigned SubIdx = MI->getOperand(3).getImm();
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assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
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assert(SubIdx != 0 && "Invalid index for insert_subreg");
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unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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assert(DstSubReg && "invalid subregister index for register");
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assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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"Insert superreg source must be in a physical register");
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assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
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"Inserted value must be in a physical register");
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DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
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if (DstSubReg == InsReg) {
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// No need to insert an identity copy instruction. If the SrcReg was
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// <undef>, we need to make sure it is alive by inserting a KILL
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if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
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MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII->get(TargetOpcode::KILL), DstReg);
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if (MI->getOperand(2).isUndef())
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MIB.addReg(InsReg, RegState::Undef);
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else
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MIB.addReg(InsReg, RegState::Kill);
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} else {
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DEBUG(dbgs() << "subreg: eliminated!\n");
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MBB->erase(MI);
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return true;
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}
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} else {
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
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if (MI->getOperand(2).isUndef())
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// If the source register being inserted is undef, then this becomes a
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// KILL.
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII->get(TargetOpcode::KILL), DstSubReg);
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else {
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bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
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MI->getDebugLoc());
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(void)Emitted;
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assert(Emitted && "Subreg and Dst must be of compatible register class");
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}
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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// INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
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if (!MI->getOperand(1).isUndef())
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
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// Transfer the kill/dead flags, if needed.
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if (MI->getOperand(0).isDead()) {
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TransferDeadFlag(MI, DstSubReg, TRI);
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} else {
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// Make sure the full DstReg is live after this replacement.
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CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
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}
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// Make sure the inserted register gets killed
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if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
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TransferKillFlag(MI, InsReg, TRI);
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}
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DEBUG({
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MachineBasicBlock::iterator dMI = MI;
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dbgs() << "subreg: " << *(--dMI) << "\n";
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});
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MBB->erase(MI);
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return true;
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}
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bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
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MachineOperand &DstMO = MI->getOperand(0);
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MachineOperand &SrcMO = MI->getOperand(1);
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@@ -387,10 +302,9 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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mi != me;) {
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MachineBasicBlock::iterator nmi = llvm::next(mi);
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MachineInstr *MI = mi;
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assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
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if (MI->isExtractSubreg()) {
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MadeChange |= LowerExtract(MI);
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} else if (MI->isInsertSubreg()) {
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MadeChange |= LowerInsert(MI);
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} else if (MI->isSubregToReg()) {
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MadeChange |= LowerSubregToReg(MI);
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} else if (MI->isCopy()) {
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