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Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-08-09 23:27:13 +00:00
parent 8fa281a471
commit d40aa24ebf
3 changed files with 47 additions and 0 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
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@ -992,6 +992,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
// Custom lower several nodes for 256-bit types.
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
@ -11172,6 +11176,9 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::CMOV_V4F32:
case X86::CMOV_V2F64:
case X86::CMOV_V2I64:
case X86::CMOV_V8F32:
case X86::CMOV_V4F64:
case X86::CMOV_V4I64:
case X86::CMOV_GR16:
case X86::CMOV_GR32:
case X86::CMOV_RFP32:

18
lib/Target/X86/X86InstrCompiler.td
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@ -759,6 +759,24 @@ let Uses = [EFLAGS], usesCustomInserter = 1 in {
[(set VR128:$dst,
(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
EFLAGS)))]>;
def CMOV_V8F32 : I<0, Pseudo,
(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
"#CMOV_V8F32 PSEUDO!",
[(set VR256:$dst,
(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
EFLAGS)))]>;
def CMOV_V4F64 : I<0, Pseudo,
(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
"#CMOV_V4F64 PSEUDO!",
[(set VR256:$dst,
(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
EFLAGS)))]>;
def CMOV_V4I64 : I<0, Pseudo,
(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
"#CMOV_V4I64 PSEUDO!",
[(set VR256:$dst,
(v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
EFLAGS)))]>;
}

22
test/CodeGen/X86/avx-select.ll Normal file
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@ -0,0 +1,22 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; CHECK: _select00
; CHECK: vmovaps
; CHECK-NEXT: LBB
define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b
%res = xor <8 x i32> %b, %selres
ret <8 x i32> %res
}
; CHECK: _select01
; CHECK: vmovaps
; CHECK-NEXT: LBB
define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b
%res = xor <4 x i64> %b, %selres
ret <4 x i64> %res
}