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Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -992,6 +992,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
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setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
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// Custom lower several nodes for 256-bit types.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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@ -11172,6 +11176,9 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::CMOV_V4F32:
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case X86::CMOV_V2F64:
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case X86::CMOV_V2I64:
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case X86::CMOV_V8F32:
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case X86::CMOV_V4F64:
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case X86::CMOV_V4I64:
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case X86::CMOV_GR16:
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case X86::CMOV_GR32:
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case X86::CMOV_RFP32:
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@ -759,6 +759,24 @@ let Uses = [EFLAGS], usesCustomInserter = 1 in {
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[(set VR128:$dst,
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(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V8F32 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V8F32 PSEUDO!",
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[(set VR256:$dst,
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(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V4F64 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V4F64 PSEUDO!",
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[(set VR256:$dst,
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(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V4I64 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V4I64 PSEUDO!",
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[(set VR256:$dst,
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(v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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}
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22
test/CodeGen/X86/avx-select.ll
Normal file
22
test/CodeGen/X86/avx-select.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: _select00
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; CHECK: vmovaps
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; CHECK-NEXT: LBB
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define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
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%cmpres = icmp eq i32 %a, 255
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%selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b
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%res = xor <8 x i32> %b, %selres
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ret <8 x i32> %res
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}
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; CHECK: _select01
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; CHECK: vmovaps
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; CHECK-NEXT: LBB
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define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
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%cmpres = icmp eq i32 %a, 255
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%selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b
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%res = xor <4 x i64> %b, %selres
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ret <4 x i64> %res
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}
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