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[AVX512] Removed special case for cmp instructions in getVectorMaskingNode. Now cmp intrinsics lower as other intrinsics through VSELECT, and then VSELECT tranforms to AND in PerformSELECTCombine.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220779 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16158,8 +16158,7 @@ static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
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return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
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}
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/// \brief Return (and \p Op, \p Mask) for compare instructions or
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/// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
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/// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
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/// necessary casting for \p Mask when lowering masking intrinsics.
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static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
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SDValue PreservedSrc, SelectionDAG &DAG) {
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@ -16180,16 +16179,6 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
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SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
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DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
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DAG.getIntPtrConstant(0));
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switch (Op.getOpcode()) {
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default: break;
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case X86ISD::PCMPEQM:
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case X86ISD::PCMPGTM:
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case X86ISD::CMPM:
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case X86ISD::CMPMU:
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return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
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}
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return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
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}
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@ -16264,9 +16253,9 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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// (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
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// (i8 (bitcast
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// (v8i1 (insert_subvector undef,
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// (v2i1 (and (PCMPEQM %a, %b),
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// (extract_subvector
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// (v8i1 (bitcast %mask)), 0))), 0))))
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// (v2i1 (vselect (extract_subvector
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// (v8i1 (bitcast %mask)), 0),
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// (PCMPEQM %a, %b), 0))))))
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EVT VT = Op.getOperand(1).getValueType();
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EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
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VT.getVectorNumElements());
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