Added MispredictPenalty to SchedMachineModel.

This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-08-08 02:44:16 +00:00
parent 3c417554ca
commit d43b5c97cf
7 changed files with 19 additions and 11 deletions

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@ -78,6 +78,11 @@ public:
unsigned HighLatency; unsigned HighLatency;
static const unsigned DefaultHighLatency = 10; static const unsigned DefaultHighLatency = 10;
// MispredictPenalty is the typical number of extra cycles the processor
// takes to recover from a branch misprediction.
unsigned MispredictPenalty;
static const unsigned DefaultMispredictPenalty = 10;
private: private:
// TODO: Add a reference to proc resource types and sched resource tables. // TODO: Add a reference to proc resource types and sched resource tables.
@ -94,13 +99,14 @@ public:
MinLatency(DefaultMinLatency), MinLatency(DefaultMinLatency),
LoadLatency(DefaultLoadLatency), LoadLatency(DefaultLoadLatency),
HighLatency(DefaultHighLatency), HighLatency(DefaultHighLatency),
MispredictPenalty(DefaultMispredictPenalty),
InstrItineraries(0) {} InstrItineraries(0) {}
// Table-gen driven ctor. // Table-gen driven ctor.
MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
const InstrItinerary *ii): const InstrItinerary *ii):
IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl), IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
InstrItineraries(ii){} MispredictPenalty(mp), InstrItineraries(ii){}
}; };
} // End llvm namespace } // End llvm namespace

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@ -27,6 +27,7 @@ class SchedMachineModel {
// (-1) inorder (0) ooo, (1): inorder +var latencies. // (-1) inorder (0) ooo, (1): inorder +var latencies.
int LoadLatency = -1; // Cycles for loads to access the cache. int LoadLatency = -1; // Cycles for loads to access the cache.
int HighLatency = -1; // Approximation of cycles for "high latency" ops. int HighLatency = -1; // Approximation of cycles for "high latency" ops.
int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
ProcessorItineraries Itineraries = NoItineraries; ProcessorItineraries Itineraries = NoItineraries;

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@ -1069,6 +1069,7 @@ def CortexA8Model : SchedMachineModel {
let LoadLatency = 2; // Optimistic load latency assuming bypass. let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the // This is overriden by OperandCycles if the
// Itineraries are queried instead. // Itineraries are queried instead.
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
let Itineraries = CortexA8Itineraries; let Itineraries = CortexA8Itineraries;
} }

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@ -1886,6 +1886,7 @@ def CortexA9Model : SchedMachineModel {
let LoadLatency = 2; // Optimistic load latency assuming bypass. let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the // This is overriden by OperandCycles if the
// Itineraries are queried instead. // Itineraries are queried instead.
let MispredictPenalty = 8; // Based on estimate of pipeline depth.
let Itineraries = CortexA9Itineraries; let Itineraries = CortexA9Itineraries;
} }

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@ -97,6 +97,9 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
if (!HasV6T2Ops && hasThumb2()) if (!HasV6T2Ops && hasThumb2())
HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
// Keep a pointer to static instruction cost data for the specified CPU.
SchedModel = getSchedModelForCPU(CPUString);
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString); InstrItins = getInstrItineraryForCPU(CPUString);
@ -179,15 +182,7 @@ ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
} }
unsigned ARMSubtarget::getMispredictionPenalty() const { unsigned ARMSubtarget::getMispredictionPenalty() const {
// If we have a reasonable estimate of the pipeline depth, then we can return SchedModel->MispredictPenalty;
// estimate the penalty of a misprediction based on that.
if (isCortexA8())
return 13;
else if (isCortexA9())
return 8;
// Otherwise, just return a sensible default.
return 10;
} }
bool ARMSubtarget::enablePostRAScheduler( bool ARMSubtarget::enablePostRAScheduler(

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@ -155,6 +155,9 @@ protected:
/// TargetTriple - What processor and OS we're targeting. /// TargetTriple - What processor and OS we're targeting.
Triple TargetTriple; Triple TargetTriple;
/// SchedModel - Processor specific instruction costs.
const MCSchedModel *SchedModel;
/// Selected instruction itineraries (one entry per itinerary class.) /// Selected instruction itineraries (one entry per itinerary class.)
InstrItineraryData InstrItins; InstrItineraryData InstrItins;

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@ -590,6 +590,7 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
if (SchedModels.hasItineraryClasses()) if (SchedModels.hasItineraryClasses())
OS << " " << PI->ItinsDef->getName(); OS << " " << PI->ItinsDef->getName();
else else