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Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,6 +78,11 @@ public:
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unsigned HighLatency;
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unsigned HighLatency;
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static const unsigned DefaultHighLatency = 10;
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static const unsigned DefaultHighLatency = 10;
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// MispredictPenalty is the typical number of extra cycles the processor
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// takes to recover from a branch misprediction.
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unsigned MispredictPenalty;
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static const unsigned DefaultMispredictPenalty = 10;
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private:
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private:
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// TODO: Add a reference to proc resource types and sched resource tables.
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// TODO: Add a reference to proc resource types and sched resource tables.
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@ -94,13 +99,14 @@ public:
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MinLatency(DefaultMinLatency),
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MinLatency(DefaultMinLatency),
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LoadLatency(DefaultLoadLatency),
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LoadLatency(DefaultLoadLatency),
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HighLatency(DefaultHighLatency),
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HighLatency(DefaultHighLatency),
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MispredictPenalty(DefaultMispredictPenalty),
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InstrItineraries(0) {}
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InstrItineraries(0) {}
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// Table-gen driven ctor.
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// Table-gen driven ctor.
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MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl,
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MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
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const InstrItinerary *ii):
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const InstrItinerary *ii):
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IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
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IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
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InstrItineraries(ii){}
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MispredictPenalty(mp), InstrItineraries(ii){}
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};
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};
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} // End llvm namespace
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} // End llvm namespace
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@ -27,6 +27,7 @@ class SchedMachineModel {
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// (-1) inorder (0) ooo, (1): inorder +var latencies.
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// (-1) inorder (0) ooo, (1): inorder +var latencies.
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int LoadLatency = -1; // Cycles for loads to access the cache.
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int LoadLatency = -1; // Cycles for loads to access the cache.
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int HighLatency = -1; // Approximation of cycles for "high latency" ops.
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int HighLatency = -1; // Approximation of cycles for "high latency" ops.
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int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
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ProcessorItineraries Itineraries = NoItineraries;
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ProcessorItineraries Itineraries = NoItineraries;
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@ -1069,6 +1069,7 @@ def CortexA8Model : SchedMachineModel {
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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// Itineraries are queried instead.
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let MispredictPenalty = 13; // Based on estimate of pipeline depth.
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let Itineraries = CortexA8Itineraries;
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let Itineraries = CortexA8Itineraries;
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}
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}
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@ -1886,6 +1886,7 @@ def CortexA9Model : SchedMachineModel {
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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// Itineraries are queried instead.
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let MispredictPenalty = 8; // Based on estimate of pipeline depth.
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let Itineraries = CortexA9Itineraries;
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let Itineraries = CortexA9Itineraries;
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}
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}
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@ -97,6 +97,9 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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if (!HasV6T2Ops && hasThumb2())
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if (!HasV6T2Ops && hasThumb2())
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HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
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HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
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// Keep a pointer to static instruction cost data for the specified CPU.
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SchedModel = getSchedModelForCPU(CPUString);
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// Initialize scheduling itinerary for the specified CPU.
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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InstrItins = getInstrItineraryForCPU(CPUString);
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@ -179,15 +182,7 @@ ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
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}
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}
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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// If we have a reasonable estimate of the pipeline depth, then we can
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return SchedModel->MispredictPenalty;
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// estimate the penalty of a misprediction based on that.
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if (isCortexA8())
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return 13;
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else if (isCortexA9())
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return 8;
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// Otherwise, just return a sensible default.
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return 10;
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}
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}
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bool ARMSubtarget::enablePostRAScheduler(
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bool ARMSubtarget::enablePostRAScheduler(
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@ -155,6 +155,9 @@ protected:
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/// TargetTriple - What processor and OS we're targeting.
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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Triple TargetTriple;
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/// SchedModel - Processor specific instruction costs.
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const MCSchedModel *SchedModel;
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/// Selected instruction itineraries (one entry per itinerary class.)
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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InstrItineraryData InstrItins;
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@ -590,6 +590,7 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
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EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
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EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
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if (SchedModels.hasItineraryClasses())
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if (SchedModels.hasItineraryClasses())
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OS << " " << PI->ItinsDef->getName();
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OS << " " << PI->ItinsDef->getName();
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else
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else
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