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Do not move any values into registers for a void return (there isn't anything).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-06-25 19:04:27 +00:00
parent 1cbb3ee75f
commit d47bbf7ce5
2 changed files with 46 additions and 40 deletions
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43
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
/// visitReturnInst - implemented with BLR
///
void ISel::visitReturnInst(ReturnInst &I) {
Value *RetVal = I.getOperand(0);
switch (getClassB(RetVal->getType())) {
case cByte: // integral return values: extend or move into r3 and return
case cShort:
case cInt:
promote32(PPC32::R3, ValueRecord(RetVal));
break;
case cFP: { // Floats & Doubles: Return in f1
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
break;
}
case cLong: {
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
break;
}
default:
visitInstruction(I);
// Only do the processing if this is a non-void return
if (I.getNumOperands() > 0) {
Value *RetVal = I.getOperand(0);
switch (getClassB(RetVal->getType())) {
case cByte: // integral return values: extend or move into r3 and return
case cShort:
case cInt:
promote32(PPC32::R3, ValueRecord(RetVal));
break;
case cFP: { // Floats & Doubles: Return in f1
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
break;
}
case cLong: {
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
break;
}
default:
visitInstruction(I);
}
}
BuildMI(BB, PPC32::BLR, 1).addImm(0);
}

43
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
/// visitReturnInst - implemented with BLR
///
void ISel::visitReturnInst(ReturnInst &I) {
Value *RetVal = I.getOperand(0);
switch (getClassB(RetVal->getType())) {
case cByte: // integral return values: extend or move into r3 and return
case cShort:
case cInt:
promote32(PPC32::R3, ValueRecord(RetVal));
break;
case cFP: { // Floats & Doubles: Return in f1
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
break;
}
case cLong: {
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
break;
}
default:
visitInstruction(I);
// Only do the processing if this is a non-void return
if (I.getNumOperands() > 0) {
Value *RetVal = I.getOperand(0);
switch (getClassB(RetVal->getType())) {
case cByte: // integral return values: extend or move into r3 and return
case cShort:
case cInt:
promote32(PPC32::R3, ValueRecord(RetVal));
break;
case cFP: { // Floats & Doubles: Return in f1
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
break;
}
case cLong: {
unsigned RetReg = getReg(RetVal);
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
break;
}
default:
visitInstruction(I);
}
}
BuildMI(BB, PPC32::BLR, 1).addImm(0);
}