6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-19 04:32:19 +00:00
Code Issues Projects Releases Wiki Activity

Do not move any values into registers for a void return (there isn't anything).

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-06-25 19:04:27 +00:00
parent 1cbb3ee75f
commit d47bbf7ce5
2 changed files with 46 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
/// visitReturnInst - implemented with BLR /// visitReturnInst - implemented with BLR
/// ///
void ISel::visitReturnInst(ReturnInst &I) { void ISel::visitReturnInst(ReturnInst &I) {
Value *RetVal = I.getOperand(0); // Only do the processing if this is a non-void return
switch (getClassB(RetVal->getType())) { if (I.getNumOperands() > 0) {
case cByte: // integral return values: extend or move into r3 and return Value *RetVal = I.getOperand(0);
case cShort: switch (getClassB(RetVal->getType())) {
case cInt: case cByte: // integral return values: extend or move into r3 and return
promote32(PPC32::R3, ValueRecord(RetVal)); case cShort:
break; case cInt:
case cFP: { // Floats & Doubles: Return in f1 promote32(PPC32::R3, ValueRecord(RetVal));
unsigned RetReg = getReg(RetVal); break;
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg); case cFP: { // Floats & Doubles: Return in f1
break; unsigned RetReg = getReg(RetVal);
} BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
case cLong: { break;
unsigned RetReg = getReg(RetVal); }
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg); case cLong: {
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1); unsigned RetReg = getReg(RetVal);
break; BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
} BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
default: break;
visitInstruction(I); }
default:
visitInstruction(I);
}
} }
BuildMI(BB, PPC32::BLR, 1).addImm(0); BuildMI(BB, PPC32::BLR, 1).addImm(0);
} }

43
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

@ -1062,26 +1062,29 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
/// visitReturnInst - implemented with BLR /// visitReturnInst - implemented with BLR
/// ///
void ISel::visitReturnInst(ReturnInst &I) { void ISel::visitReturnInst(ReturnInst &I) {
Value *RetVal = I.getOperand(0); // Only do the processing if this is a non-void return
switch (getClassB(RetVal->getType())) { if (I.getNumOperands() > 0) {
case cByte: // integral return values: extend or move into r3 and return Value *RetVal = I.getOperand(0);
case cShort: switch (getClassB(RetVal->getType())) {
case cInt: case cByte: // integral return values: extend or move into r3 and return
promote32(PPC32::R3, ValueRecord(RetVal)); case cShort:
break; case cInt:
case cFP: { // Floats & Doubles: Return in f1 promote32(PPC32::R3, ValueRecord(RetVal));
unsigned RetReg = getReg(RetVal); break;
BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg); case cFP: { // Floats & Doubles: Return in f1
break; unsigned RetReg = getReg(RetVal);
} BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
case cLong: { break;
unsigned RetReg = getReg(RetVal); }
BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg); case cLong: {
BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1); unsigned RetReg = getReg(RetVal);
break; BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
} BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
default: break;
visitInstruction(I); }
default:
visitInstruction(I);
}
} }
BuildMI(BB, PPC32::BLR, 1).addImm(0); BuildMI(BB, PPC32::BLR, 1).addImm(0);
} }