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Properly pseudo-ize MOVCCr and MOVCCs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-03-10 23:56:09 +00:00
parent c9f2f61d34
commit d4a16ad85d
4 changed files with 41 additions and 32 deletions
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7
utils/TableGen/ARMDecoderEmitter.cpp
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@@ -1606,13 +1606,12 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
// MOVCCr, MOVCCs, MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and
// MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and
// FNEGDcc are used in the compiler to implement conditional moves.
// We can ignore them in favor of their more generic versions of
// instructions. See also SDNode *ARMDAGToDAGISel::Select(SDValue Op).
if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" ||
Name == "MOVCCi16" || Name == "FCPYScc" || Name == "FCPYDcc" ||
Name == "FNEGScc" || Name == "FNEGDcc")
if (Name == "MOVCCi" || Name == "MOVCCi16" || Name == "FCPYScc" ||
Name == "FCPYDcc" || Name == "FNEGScc" || Name == "FNEGDcc")
return false;
// Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc.