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[mips][FastISel] Implement srem/urem and sdiv/udiv instructions.
Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
parent
e490b7733a
commit
d4b311fb43
@ -103,6 +103,7 @@ private:
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bool selectTrunc(const Instruction *I);
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bool selectIntExt(const Instruction *I);
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bool selectShift(const Instruction *I);
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bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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@ -1471,6 +1472,50 @@ unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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return Success ? DestReg : 0;
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}
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bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
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EVT DestEVT = TLI.getValueType(I->getType(), true);
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if (!DestEVT.isSimple())
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return false;
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MVT DestVT = DestEVT.getSimpleVT();
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if (DestVT != MVT::i32)
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return false;
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unsigned DivOpc;
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switch (ISDOpcode) {
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default:
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return false;
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case ISD::SDIV:
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case ISD::SREM:
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DivOpc = Mips::SDIV;
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break;
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case ISD::UDIV:
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case ISD::UREM:
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DivOpc = Mips::UDIV;
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break;
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}
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unsigned Src0Reg = getRegForValue(I->getOperand(0));
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unsigned Src1Reg = getRegForValue(I->getOperand(1));
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if (!Src0Reg || !Src1Reg)
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return false;
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emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
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emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
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unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
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if (!ResultReg)
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return false;
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unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
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? Mips::MFHI
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: Mips::MFLO;
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emitInst(MFOpc, ResultReg);
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updateValueMap(I, ResultReg);
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return true;
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}
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bool MipsFastISel::selectShift(const Instruction *I) {
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MVT RetVT;
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@ -1556,6 +1601,22 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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return selectLoad(I);
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case Instruction::Store:
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return selectStore(I);
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case Instruction::SDiv:
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if (!selectBinaryOp(I, ISD::SDIV))
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return selectDivRem(I, ISD::SDIV);
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return true;
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case Instruction::UDiv:
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if (!selectBinaryOp(I, ISD::UDIV))
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return selectDivRem(I, ISD::UDIV);
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return true;
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case Instruction::SRem:
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if (!selectBinaryOp(I, ISD::SREM))
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return selectDivRem(I, ISD::SREM);
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return true;
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case Instruction::URem:
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if (!selectBinaryOp(I, ISD::UREM))
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return selectDivRem(I, ISD::UREM);
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return true;
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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55
test/CodeGen/Mips/Fast-ISel/div1.ll
Normal file
55
test/CodeGen/Mips/Fast-ISel/div1.ll
Normal file
@ -0,0 +1,55 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
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@sj = global i32 200000, align 4
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@sk = global i32 -47, align 4
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@uj = global i32 200000, align 4
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@uk = global i32 43, align 4
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@si = common global i32 0, align 4
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@ui = common global i32 0, align 4
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define void @divs() {
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; CHECK-LABEL: divs:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: div $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @sj, align 4
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%2 = load i32, i32* @sk, align 4
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%div = sdiv i32 %1, %2
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store i32 %div, i32* @si, align 4
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ret void
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}
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define void @divu() {
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; CHECK-LABEL: divu:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: divu $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mflo $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @uj, align 4
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%2 = load i32, i32* @uk, align 4
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%div = udiv i32 %1, %2
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store i32 %div, i32* @ui, align 4
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ret void
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}
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56
test/CodeGen/Mips/Fast-ISel/rem1.ll
Normal file
56
test/CodeGen/Mips/Fast-ISel/rem1.ll
Normal file
@ -0,0 +1,56 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
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; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
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; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s
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@sj = global i32 200, align 4
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@sk = global i32 -47, align 4
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@uj = global i32 200, align 4
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@uk = global i32 43, align 4
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@si = common global i32 0, align 4
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@ui = common global i32 0, align 4
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define void @rems() {
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; CHECK-LABEL: rems:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: div $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @sj, align 4
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%2 = load i32, i32* @sk, align 4
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%rem = srem i32 %1, %2
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store i32 %rem, i32* @si, align 4
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ret void
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}
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; Function Attrs: noinline nounwind
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define void @remu() {
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; CHECK-LABEL: remu:
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; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
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; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
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; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
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; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
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; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]])
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; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]])
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; CHECK-DAG: divu $zero, $[[J]], $[[K]]
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; CHECK_DAG: teq $[[K]], $zero, 7
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; CHECK-DAG: mfhi $[[RESULT:[0-9]+]]
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; CHECK: sw $[[RESULT]], 0($[[I_ADDR]])
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%1 = load i32, i32* @uj, align 4
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%2 = load i32, i32* @uk, align 4
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%rem = urem i32 %1, %2
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store i32 %rem, i32* @ui, align 4
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ret void
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}
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