Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to

compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-06-14 01:16:45 +00:00
parent 4654e58a64
commit d4b48b283c
2 changed files with 76 additions and 6 deletions

View File

@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
#include "MipsAnalyzeImmediate.h"
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
#include "MipsMachineFunction.h"
@ -505,3 +506,58 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
return false;
}
/// Return the number of bytes of code the specified instruction may be.
unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default:
return MI->getDesc().getSize();
case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
const MachineFunction *MF = MI->getParent()->getParent();
const char *AsmStr = MI->getOperand(0).getSymbolName();
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
}
}
}
unsigned
llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
MachineBasicBlock& MBB,
MachineBasicBlock::iterator II, DebugLoc DL,
bool LastInstrIsADDiu,
MipsAnalyzeImmediate::Inst *LastInst) {
MipsAnalyzeImmediate AnalyzeImm;
unsigned Size = IsN64 ? 64 : 32;
unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
const MipsAnalyzeImmediate::InstSeq &Seq =
AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
if (LastInst && (Seq.size() == 1)) {
*LastInst = *Inst;
return 0;
}
// The first instruction can be a LUi, which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register
// operand.
if (Inst->Opc == LUi)
BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
.addImm(SignExtend64<16>(Inst->ImmOpnd));
else
BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
.addImm(SignExtend64<16>(Inst->ImmOpnd));
// Build the remaining instructions in Seq. Skip the last instruction if
// LastInst is not 0.
for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
.addImm(SignExtend64<16>(Inst->ImmOpnd));
if (LastInst)
*LastInst = *Inst;
return Seq.size() - !!LastInst;
}

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@ -15,6 +15,7 @@
#define MIPSINSTRUCTIONINFO_H
#include "Mips.h"
#include "MipsAnalyzeImmediate.h"
#include "MipsRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetInstrInfo.h"
@ -24,12 +25,6 @@
namespace llvm {
namespace Mips {
/// GetOppositeBranchOpc - Return the inverse of the specified
/// opcode, e.g. turning BEQ to BNE.
unsigned GetOppositeBranchOpc(unsigned Opc);
}
class MipsInstrInfo : public MipsGenInstrInfo {
MipsTargetMachine &TM;
bool IsN64;
@ -109,8 +104,27 @@ public:
/// Insert nop instruction when hazard condition is found
virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
/// Return the number of bytes of code the specified instruction may be.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
};
namespace Mips {
/// GetOppositeBranchOpc - Return the inverse of the specified
/// opcode, e.g. turning BEQ to BNE.
unsigned GetOppositeBranchOpc(unsigned Opc);
/// Emit a series of instructions to load an immediate. All instructions
/// except for the last one are emitted. The function returns the number of
/// MachineInstrs generated. The opcode-immediate pair of the last
/// instruction is returned in LastInst, if it is not 0.
unsigned
loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
MachineBasicBlock& MBB, MachineBasicBlock::iterator II,
DebugLoc DL, bool LastInstrIsADDiu,
MipsAnalyzeImmediate::Inst *LastInst);
}
}
#endif