mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
2ea20154ce
commit
d4b4cf524b
@ -61,9 +61,6 @@ let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_2Result_Intrinsic
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: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
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[LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
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class Neon_CvtFxToFP_Intrinsic
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: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_CvtFPToFx_Intrinsic
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@ -315,15 +312,6 @@ def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
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def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
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def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
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// Vector Transpose.
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def int_arm_neon_vtrn : Neon_2Result_Intrinsic;
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// Vector Interleave (vzip).
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def int_arm_neon_vzip : Neon_2Result_Intrinsic;
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// Vector Deinterleave (vuzp).
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def int_arm_neon_vuzp : Neon_2Result_Intrinsic;
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let TargetPrefix = "arm" in {
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// De-interleaving vector loads from N-element structures.
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@ -1415,63 +1415,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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N->getOperand(4), N->getOperand(5), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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EVT VT = N->getValueType(0);
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unsigned Opc = 0;
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// Match intrinsics that return multiple values.
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switch (IntNo) {
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default: break;
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case Intrinsic::arm_neon_vtrn:
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switch (VT.getSimpleVT().SimpleTy) {
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default: return NULL;
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case MVT::v8i8: Opc = ARM::VTRNd8; break;
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case MVT::v4i16: Opc = ARM::VTRNd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VTRNd32; break;
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case MVT::v16i8: Opc = ARM::VTRNq8; break;
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case MVT::v8i16: Opc = ARM::VTRNq16; break;
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case MVT::v4f32:
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case MVT::v4i32: Opc = ARM::VTRNq32; break;
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}
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return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
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N->getOperand(2));
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case Intrinsic::arm_neon_vuzp:
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switch (VT.getSimpleVT().SimpleTy) {
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default: return NULL;
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case MVT::v8i8: Opc = ARM::VUZPd8; break;
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case MVT::v4i16: Opc = ARM::VUZPd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VUZPd32; break;
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case MVT::v16i8: Opc = ARM::VUZPq8; break;
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case MVT::v8i16: Opc = ARM::VUZPq16; break;
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case MVT::v4f32:
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case MVT::v4i32: Opc = ARM::VUZPq32; break;
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}
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return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
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N->getOperand(2));
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case Intrinsic::arm_neon_vzip:
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switch (VT.getSimpleVT().SimpleTy) {
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default: return NULL;
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case MVT::v8i8: Opc = ARM::VZIPd8; break;
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case MVT::v4i16: Opc = ARM::VZIPd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VZIPd32; break;
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case MVT::v16i8: Opc = ARM::VZIPq8; break;
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case MVT::v8i16: Opc = ARM::VZIPq16; break;
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case MVT::v4f32:
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case MVT::v4i32: Opc = ARM::VZIPq32; break;
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}
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return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
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N->getOperand(2));
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}
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break;
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}
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}
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return SelectCode(Op);
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@ -1,117 +0,0 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
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%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
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%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
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%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
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define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtrni8:
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;CHECK: vtrn.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
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%tmp6 = add <8 x i8> %tmp4, %tmp5
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ret <8 x i8> %tmp6
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}
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define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vtrni16:
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;CHECK: vtrn.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
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%tmp6 = add <4 x i16> %tmp4, %tmp5
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ret <4 x i16> %tmp6
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}
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define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vtrni32:
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;CHECK: vtrn.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
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%tmp6 = add <2 x i32> %tmp4, %tmp5
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ret <2 x i32> %tmp6
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}
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define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vtrnf:
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;CHECK: vtrn.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
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%tmp6 = add <2 x float> %tmp4, %tmp5
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ret <2 x float> %tmp6
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}
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define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vtrnQi8:
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;CHECK: vtrn.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
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%tmp6 = add <16 x i8> %tmp4, %tmp5
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ret <16 x i8> %tmp6
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}
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define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vtrnQi16:
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;CHECK: vtrn.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
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%tmp6 = add <8 x i16> %tmp4, %tmp5
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ret <8 x i16> %tmp6
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}
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define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vtrnQi32:
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;CHECK: vtrn.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
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%tmp6 = add <4 x i32> %tmp4, %tmp5
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ret <4 x i32> %tmp6
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}
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define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vtrnQf:
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;CHECK: vtrn.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
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%tmp6 = add <4 x float> %tmp4, %tmp5
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ret <4 x float> %tmp6
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}
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declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float>, <4 x float>) nounwind readnone
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@ -1,117 +0,0 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
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%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
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%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
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%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
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define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vuzpi8:
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;CHECK: vuzp.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vuzp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
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%tmp6 = add <8 x i8> %tmp4, %tmp5
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ret <8 x i8> %tmp6
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}
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define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vuzpi16:
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;CHECK: vuzp.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vuzp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
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%tmp6 = add <4 x i16> %tmp4, %tmp5
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ret <4 x i16> %tmp6
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}
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define <2 x i32> @vuzpi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vuzpi32:
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;CHECK: vuzp.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vuzp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
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%tmp6 = add <2 x i32> %tmp4, %tmp5
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ret <2 x i32> %tmp6
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}
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define <2 x float> @vuzpf(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vuzpf:
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;CHECK: vuzp.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vuzp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
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%tmp6 = add <2 x float> %tmp4, %tmp5
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ret <2 x float> %tmp6
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}
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define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vuzpQi8:
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;CHECK: vuzp.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vuzp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
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%tmp6 = add <16 x i8> %tmp4, %tmp5
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ret <16 x i8> %tmp6
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}
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define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vuzpQi16:
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;CHECK: vuzp.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vuzp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
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%tmp6 = add <8 x i16> %tmp4, %tmp5
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ret <8 x i16> %tmp6
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}
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define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vuzpQi32:
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;CHECK: vuzp.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vuzp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
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%tmp6 = add <4 x i32> %tmp4, %tmp5
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ret <4 x i32> %tmp6
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}
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define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vuzpQf:
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;CHECK: vuzp.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vuzp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
|
||||
%tmp6 = add <4 x float> %tmp4, %tmp5
|
||||
ret <4 x float> %tmp6
|
||||
}
|
||||
|
||||
declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vuzp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vuzp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vuzp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vuzp.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
||||
|
||||
declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vuzp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vuzp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vuzp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vuzp.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
||||
@ -1,117 +0,0 @@
|
||||
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
|
||||
|
||||
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
|
||||
%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
|
||||
%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
|
||||
%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
|
||||
|
||||
%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
|
||||
%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
|
||||
%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
|
||||
%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
|
||||
|
||||
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vzipi8:
|
||||
;CHECK: vzip.8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vzip.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
|
||||
%tmp6 = add <8 x i8> %tmp4, %tmp5
|
||||
ret <8 x i8> %tmp6
|
||||
}
|
||||
|
||||
define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vzipi16:
|
||||
;CHECK: vzip.16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vzip.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
|
||||
%tmp6 = add <4 x i16> %tmp4, %tmp5
|
||||
ret <4 x i16> %tmp6
|
||||
}
|
||||
|
||||
define <2 x i32> @vzipi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vzipi32:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vzip.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
|
||||
%tmp6 = add <2 x i32> %tmp4, %tmp5
|
||||
ret <2 x i32> %tmp6
|
||||
}
|
||||
|
||||
define <2 x float> @vzipf(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vzipf:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <2 x float>* %A
|
||||
%tmp2 = load <2 x float>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vzip.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
|
||||
%tmp6 = add <2 x float> %tmp4, %tmp5
|
||||
ret <2 x float> %tmp6
|
||||
}
|
||||
|
||||
define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
||||
;CHECK: vzipQi8:
|
||||
;CHECK: vzip.8
|
||||
%tmp1 = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vzip.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
|
||||
%tmp6 = add <16 x i8> %tmp4, %tmp5
|
||||
ret <16 x i8> %tmp6
|
||||
}
|
||||
|
||||
define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
||||
;CHECK: vzipQi16:
|
||||
;CHECK: vzip.16
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vzip.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
|
||||
%tmp6 = add <8 x i16> %tmp4, %tmp5
|
||||
ret <8 x i16> %tmp6
|
||||
}
|
||||
|
||||
define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
||||
;CHECK: vzipQi32:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i32>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vzip.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
|
||||
%tmp6 = add <4 x i32> %tmp4, %tmp5
|
||||
ret <4 x i32> %tmp6
|
||||
}
|
||||
|
||||
define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
|
||||
;CHECK: vzipQf:
|
||||
;CHECK: vzip.32
|
||||
%tmp1 = load <4 x float>* %A
|
||||
%tmp2 = load <4 x float>* %B
|
||||
%tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vzip.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
|
||||
%tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
|
||||
%tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
|
||||
%tmp6 = add <4 x float> %tmp4, %tmp5
|
||||
ret <4 x float> %tmp6
|
||||
}
|
||||
|
||||
declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vzip.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vzip.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vzip.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vzip.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
||||
|
||||
declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vzip.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vzip.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vzip.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vzip.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
||||
Loading…
Reference in New Issue
Block a user