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https://github.com/c64scene-ar/llvm-6502.git
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R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.
Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case and taking them in account for scheduling is difficult for no real benefit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176488 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
cae6801b7d
commit
d4c3e56692
@ -23,7 +23,6 @@ class AMDGPUTargetMachine;
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// R600 Passes
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FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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FunctionPass *createR600LowerConstCopy(TargetMachine &tm);
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// SI Passes
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FunctionPass *createSIAnnotateControlFlowPass();
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@ -143,7 +143,6 @@ bool AMDGPUPassConfig::addPreEmitPass() {
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addPass(createAMDGPUCFGStructurizerPass(*TM));
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addPass(createR600ExpandSpecialInstrsPass(*TM));
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addPass(&FinalizeMachineBundlesID);
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addPass(createR600LowerConstCopy(*TM));
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} else {
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addPass(createSILowerControlFlowPass(*TM));
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}
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@ -150,7 +150,13 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
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MI->getOperand(1).getImm());
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break;
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case AMDGPU::CONST_COPY: {
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MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
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MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
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TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
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MI->getOperand(1).getImm());
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break;
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}
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case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
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@ -1650,17 +1650,18 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1,
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// Constant Buffer Addressing Support
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
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let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
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def CONST_COPY : Instruction {
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let OutOperandList = (outs R600_Reg32:$dst);
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let InOperandList = (ins i32imm:$src);
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let Pattern = [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
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let Pattern =
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[(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
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let AsmString = "CONST_COPY";
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let neverHasSideEffects = 1;
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let isAsCheapAsAMove = 1;
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let Itinerary = NullALU;
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}
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} // end isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
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} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
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def TEX_VTX_CONSTBUF :
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InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
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@ -1,222 +0,0 @@
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//===-- R600LowerConstCopy.cpp - Propagate ConstCopy / lower them to MOV---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass is intended to handle remaining ConstCopy pseudo MachineInstr.
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/// ISel will fold each Const Buffer read inside scalar ALU. However it cannot
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/// fold them inside vector instruction, like DOT4 or Cube ; ISel emits
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/// ConstCopy instead. This pass (executed after ExpandingSpecialInstr) will try
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/// to fold them if possible or replace them by MOV otherwise.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalValue.h"
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namespace llvm {
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class R600LowerConstCopy : public MachineFunctionPass {
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private:
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static char ID;
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const R600InstrInfo *TII;
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struct ConstPairs {
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unsigned XYPair;
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unsigned ZWPair;
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};
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bool canFoldInBundle(ConstPairs &UsedConst, unsigned ReadConst) const;
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public:
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R600LowerConstCopy(TargetMachine &tm);
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "R600 Eliminate Symbolic Operand"; }
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};
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char R600LowerConstCopy::ID = 0;
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R600LowerConstCopy::R600LowerConstCopy(TargetMachine &tm) :
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MachineFunctionPass(ID),
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TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo()))
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{
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}
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bool R600LowerConstCopy::canFoldInBundle(ConstPairs &UsedConst,
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unsigned ReadConst) const {
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unsigned ReadConstChan = ReadConst & 3;
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unsigned ReadConstIndex = ReadConst & (~3);
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if (ReadConstChan < 2) {
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if (!UsedConst.XYPair) {
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UsedConst.XYPair = ReadConstIndex;
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}
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return UsedConst.XYPair == ReadConstIndex;
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} else {
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if (!UsedConst.ZWPair) {
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UsedConst.ZWPair = ReadConstIndex;
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}
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return UsedConst.ZWPair == ReadConstIndex;
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}
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}
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static bool isControlFlow(const MachineInstr &MI) {
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return (MI.getOpcode() == AMDGPU::IF_PREDICATE_SET) ||
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(MI.getOpcode() == AMDGPU::ENDIF) ||
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(MI.getOpcode() == AMDGPU::ELSE) ||
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(MI.getOpcode() == AMDGPU::WHILELOOP) ||
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(MI.getOpcode() == AMDGPU::BREAK);
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}
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bool R600LowerConstCopy::runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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DenseMap<unsigned, MachineInstr *> RegToConstIndex;
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for (MachineBasicBlock::instr_iterator I = MBB.instr_begin(),
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E = MBB.instr_end(); I != E;) {
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if (I->getOpcode() == AMDGPU::CONST_COPY) {
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MachineInstr &MI = *I;
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I = llvm::next(I);
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unsigned DstReg = MI.getOperand(0).getReg();
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DenseMap<unsigned, MachineInstr *>::iterator SrcMI =
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RegToConstIndex.find(DstReg);
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if (SrcMI != RegToConstIndex.end()) {
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SrcMI->second->eraseFromParent();
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RegToConstIndex.erase(SrcMI);
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}
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MachineInstr *NewMI =
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TII->buildDefaultInstruction(MBB, &MI, AMDGPU::MOV,
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MI.getOperand(0).getReg(), AMDGPU::ALU_CONST);
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TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
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MI.getOperand(1).getImm());
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RegToConstIndex[DstReg] = NewMI;
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MI.eraseFromParent();
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continue;
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}
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std::vector<unsigned> Defs;
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// We consider all Instructions as bundled because algorithm that handle
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// const read port limitations inside an IG is still valid with single
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// instructions.
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std::vector<MachineInstr *> Bundle;
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if (I->isBundle()) {
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unsigned BundleSize = I->getBundleSize();
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for (unsigned i = 0; i < BundleSize; i++) {
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I = llvm::next(I);
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Bundle.push_back(I);
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}
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} else if (TII->isALUInstr(I->getOpcode())){
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Bundle.push_back(I);
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} else if (isControlFlow(*I)) {
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RegToConstIndex.clear();
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I = llvm::next(I);
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continue;
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} else {
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MachineInstr &MI = *I;
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for (MachineInstr::mop_iterator MOp = MI.operands_begin(),
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MOpE = MI.operands_end(); MOp != MOpE; ++MOp) {
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MachineOperand &MO = *MOp;
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if (!MO.isReg())
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continue;
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if (MO.isDef()) {
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Defs.push_back(MO.getReg());
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} else {
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// Either a TEX or an Export inst, prevent from erasing def of used
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// operand
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RegToConstIndex.erase(MO.getReg());
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for (MCSubRegIterator SR(MO.getReg(), &TII->getRegisterInfo());
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SR.isValid(); ++SR) {
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RegToConstIndex.erase(*SR);
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}
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}
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}
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}
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R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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for(std::vector<MachineInstr *>::iterator It = Bundle.begin(),
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ItE = Bundle.end(); It != ItE; ++It) {
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MachineInstr *MI = *It;
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if (TII->isPredicated(MI)) {
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// We don't want to erase previous assignment
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RegToConstIndex.erase(MI->getOperand(0).getReg());
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} else {
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int WriteIDX = TII->getOperandIdx(MI->getOpcode(), R600Operands::WRITE);
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if (WriteIDX < 0 || MI->getOperand(WriteIDX).getImm())
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Defs.push_back(MI->getOperand(0).getReg());
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}
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}
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ConstPairs CP = {0,0};
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for (unsigned SrcOp = 0; SrcOp < 3; SrcOp++) {
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for(std::vector<MachineInstr *>::iterator It = Bundle.begin(),
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ItE = Bundle.end(); It != ItE; ++It) {
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MachineInstr *MI = *It;
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int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[SrcOp][0]);
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if (SrcIdx < 0)
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continue;
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MachineOperand &MO = MI->getOperand(SrcIdx);
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DenseMap<unsigned, MachineInstr *>::iterator SrcMI =
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RegToConstIndex.find(MO.getReg());
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if (SrcMI != RegToConstIndex.end()) {
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MachineInstr *CstMov = SrcMI->second;
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int ConstMovSel =
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TII->getOperandIdx(CstMov->getOpcode(), R600Operands::SRC0_SEL);
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unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm();
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if (MI->isInsideBundle() && canFoldInBundle(CP, ConstIndex)) {
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TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex);
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MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST);
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} else {
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RegToConstIndex.erase(SrcMI);
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}
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}
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}
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}
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for (std::vector<unsigned>::iterator It = Defs.begin(), ItE = Defs.end();
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It != ItE; ++It) {
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DenseMap<unsigned, MachineInstr *>::iterator SrcMI =
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RegToConstIndex.find(*It);
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if (SrcMI != RegToConstIndex.end()) {
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SrcMI->second->eraseFromParent();
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RegToConstIndex.erase(SrcMI);
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}
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}
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I = llvm::next(I);
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}
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if (MBB.succ_empty()) {
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for (DenseMap<unsigned, MachineInstr *>::iterator
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DI = RegToConstIndex.begin(), DE = RegToConstIndex.end();
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DI != DE; ++DI) {
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DI->second->eraseFromParent();
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}
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}
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}
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return false;
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}
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FunctionPass *createR600LowerConstCopy(TargetMachine &tm) {
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return new R600LowerConstCopy(tm);
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}
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}
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