diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index cedbe3fed09..8867275d619 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -422,40 +422,6 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
   if (CloseParen) O << ")";
 }
 
-static bool isLoadInstruction (const MachineInstr *MI) {
-  switch (MI->getOpcode ()) {
-  case V8::LDSB:
-  case V8::LDSH:
-  case V8::LDUB:
-  case V8::LDUH:
-  case V8::LD:
-  case V8::LDD:
-  case V8::LDFrr:
-  case V8::LDFri:
-  case V8::LDDFrr:
-  case V8::LDDFri:
-    return true;
-  default:
-    return false;
-  }
-}
-
-static bool isStoreInstruction (const MachineInstr *MI) {
-  switch (MI->getOpcode ()) {
-  case V8::STB:
-  case V8::STH:
-  case V8::ST:
-  case V8::STD:
-  case V8::STFrr:
-  case V8::STFri:
-  case V8::STDFrr:
-  case V8::STDFri:
-    return true;
-  default:
-    return false;
-  }
-}
-
 static bool isPseudoInstruction (const MachineInstr *MI) {
   switch (MI->getOpcode ()) {
   case V8::PHI:
@@ -507,23 +473,6 @@ void SparcV8AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
 
   O << Desc.Name << " ";
 
-  // Printing memory instructions is a special case.
-  // for loads:  %dest = op %base, offset --> op [%base + offset], %dest
-  // for stores: op %base, offset, %src   --> op %src, [%base + offset]
-  if (isLoadInstruction (MI)) {
-    printBaseOffsetPair (MI, 1);
-    O << ", ";
-    printOperand (MI, 0);
-    O << "\n";
-    return;
-  } else if (isStoreInstruction (MI)) {
-    printOperand (MI, 2);
-    O << ", ";
-    printBaseOffsetPair (MI, 0);
-    O << "\n";
-    return;
-  }
-
   // print non-immediate, non-register-def operands
   // then print immediate operands
   // then print register-def operands.
diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td
index b63e39148fb..e30edce83c7 100644
--- a/lib/Target/Sparc/SparcInstrFormats.td
+++ b/lib/Target/Sparc/SparcInstrFormats.td
@@ -73,14 +73,14 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
   let Inst{4-0}  = rs2;
 }
 
-class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
+class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
   bits<13> simm13;
 
   dag OperandList = ops;
+  let AsmString   = asmstr;
   
   let op         = opVal;
   let op3        = op3val;
-  let Name       = name;
 
   let Inst{13}   = 1;     // i field = 1
   let Inst{12-0} = simm13;
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 9cb9811dc5b..6bf5f27d18c 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -51,80 +51,99 @@ def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
   let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
     def RET : F3_2<2, 0b111000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ret">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "ret $b, $c, $dst">;
   let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
-    def RETL: F3_2<2, 0b111000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "retl">;
+    def RETL: F3_2<2, 0b111000, (ops),
+                   "retl">;
 }
 // CMP is a special case of SUBCC where destination is ignored, by setting it to
 // %g0 (hardwired zero).
 // FIXME: should keep track of the fact that it defs the integer condition codes
 let rd = 0 in
   def CMPri: F3_2<2, 0b010100,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "cmp">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "cmp $b, $c, $dst">;
 
 // Section B.1 - Load Integer Instructions, p. 90
 def LDSB: F3_2<3, 0b001001,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsb">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldsb [$b+$c], $dst">;
 def LDSH: F3_2<3, 0b001010,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsh">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldsh [$b+$c], $dst">;
 def LDUB: F3_2<3, 0b000001,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldub">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldub [$b+$c], $dst">;
 def LDUH: F3_2<3, 0b000010,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "lduh">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "lduh [$b+$c], $dst">;
 def LD  : F3_2<3, 0b000000,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ld [$b+$c], $dst">;
 def LDD : F3_2<3, 0b000011,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldd [$b+$c], $dst">;
 
 // Section B.2 - Load Floating-point Instructions, p. 92
 def LDFrr  : F3_1<3, 0b100000,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ld $b, $c, $dst">;
+                  "ld [$b+$c], $dst">;
 def LDFri  : F3_2<3, 0b100000,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ld [$b+$c], $dst">;
 def LDDFrr : F3_1<3, 0b100011,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ldd $b, $c, $dst">;
+                  "ldd [$b+$c], $dst">;
 def LDDFri : F3_2<3, 0b100011,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ldd [$b+$c], $dst">;
 def LDFSRrr: F3_1<3, 0b100001,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ld $b, $c, $dst">;
+                  "ld [$b+$c], $dst">;
 def LDFSRri: F3_2<3, 0b100001,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ld [$b+$c], $dst">;
 
 // Section B.4 - Store Integer Instructions, p. 95
 def STB : F3_2<3, 0b000101,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "stb">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "stb $src, [$base+$offset]">;
 def STH : F3_2<3, 0b000110,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sth">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "sth $src, [$base+$offset]">;
 def ST  : F3_2<3, 0b000100,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "st $src, [$base+$offset]">;
 def STD : F3_2<3, 0b000111,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "std $src, [$base+$offset]">;
 
 // Section B.5 - Store Floating-point Instructions, p. 97
 def STFrr   : F3_1<3, 0b100100,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "st $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "st $src, [$base+$offset]">;
 def STFri   : F3_2<3, 0b100100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "st $src, [$base+$offset]">;
 def STDFrr  : F3_1<3, 0b100111,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "std $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "std  $src, [$base+$offset]">;
 def STDFri  : F3_2<3, 0b100111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "std $src, [$base+$offset]">;
 def STFSRrr : F3_1<3, 0b100101,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "st $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "st $src, [$base+$offset]">;
 def STFSRri : F3_2<3, 0b100101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "st $src, [$base+$offset]">;
 def STDFQrr : F3_1<3, 0b100110,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "std $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "std $src, [$base+$offset]">;
 def STDFQri : F3_2<3, 0b100110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "std $src, [$base+$offset]">;
 
 // Section B.9 - SETHI Instruction, p. 104
 def SETHIi: F2_1<0b100, "sethi">;
@@ -139,179 +158,212 @@ def ANDrr   : F3_1<2, 0b000001,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "and $b, $c, $dst">;
 def ANDri   : F3_2<2, 0b000001,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "and">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "and $b, $c, $dst">;
 def ANDCCrr : F3_1<2, 0b010001,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andcc $b, $c, $dst">;
 def ANDCCri : F3_2<2, 0b010001,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andcc $b, $c, $dst">;
 def ANDNrr  : F3_1<2, 0b000101,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andn $b, $c, $dst">;
 def ANDNri  : F3_2<2, 0b000101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andn">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andn $b, $c, $dst">;
 def ANDNCCrr: F3_1<2, 0b010101,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andncc $b, $c, $dst">;
 def ANDNCCri: F3_2<2, 0b010101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andncc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andncc $b, $c, $dst">;
 def ORrr    : F3_1<2, 0b000010,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "or $b, $c, $dst">;
 def ORri    : F3_2<2, 0b000010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "or">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "or $b, $c, $dst">;
 def ORCCrr  : F3_1<2, 0b010010,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orcc $b, $c, $dst">;
 def ORCCri  : F3_2<2, 0b010010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orcc $b, $c, $dst">;
 def ORNrr   : F3_1<2, 0b000110,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orn $b, $c, $dst">;
 def ORNri   : F3_2<2, 0b000110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orn">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orn $b, $c, $dst">;
 def ORNCCrr : F3_1<2, 0b010110,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orncc $b, $c, $dst">;
 def ORNCCri : F3_2<2, 0b010110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orncc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orncc $b, $c, $dst">;
 def XORrr   : F3_1<2, 0b000011,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xor $b, $c, $dst">;
 def XORri   : F3_2<2, 0b000011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xor">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xor $b, $c, $dst">;
 def XORCCrr : F3_1<2, 0b010011,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xorcc $b, $c, $dst">;
 def XORCCri : F3_2<2, 0b010011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xorcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xorcc $b, $c, $dst">;
 def XNORrr  : F3_1<2, 0b000111,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xnor $b, $c, $dst">;
 def XNORri  : F3_2<2, 0b000111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnor">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xnor $b, $c, $dst">;
 def XNORCCrr: F3_1<2, 0b010111,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xnorcc $b, $c, $dst">;
 def XNORCCri: F3_2<2, 0b010111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnorcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xnorcc $b, $c, $dst">;
 
 // Section B.12 - Shift Instructions, p. 107
 def SLLrr : F3_1<2, 0b100101,
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                  "sll $b, $c, $dst">;
 def SLLri : F3_2<2, 0b100101,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sll">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "sll $b, $c, $dst">;
 def SRLrr : F3_1<2, 0b100110, 
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "srl $b, $c, $dst">;
 def SRLri : F3_2<2, 0b100110,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "srl">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "srl $b, $c, $dst">;
 def SRArr : F3_1<2, 0b100111, 
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "sra $b, $c, $dst">;
 def SRAri : F3_2<2, 0b100111,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sra">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "sla $b, $c, $dst">;
 
 // Section B.13 - Add Instructions, p. 108
 def ADDrr   : F3_1<2, 0b000000, 
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "add $b, $c, $dst">;
 def ADDri   : F3_2<2, 0b000000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "add">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "add $b, $c, $dst">;
 def ADDCCrr : F3_1<2, 0b010000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addcc $b, $c, $dst">;
 def ADDCCri : F3_2<2, 0b010000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addcc $b, $c, $dst">;
 def ADDXrr  : F3_1<2, 0b001000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addx $b, $c, $dst">;
 def ADDXri  : F3_2<2, 0b001000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addx">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addx $b, $c, $dst">;
 def ADDXCCrr: F3_1<2, 0b011000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addxcc $b, $c, $dst">;
 def ADDXCCri: F3_2<2, 0b011000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addxcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addxcc $b, $c, $dst">;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, 
-                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "sub $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "sub $b, $c, $dst">;
 def SUBri   : F3_2<2, 0b000100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sub">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "sub $b, $c, $dst">;
 def SUBCCrr : F3_1<2, 0b010100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subcc $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subcc $b, $c, $dst">;
 def SUBCCri : F3_2<2, 0b010100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subcc $b, $c, $dst">;
 def SUBXrr  : F3_1<2, 0b001100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subx $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subx $b, $c, $dst">;
 def SUBXri  : F3_2<2, 0b001100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subx">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subx $b, $c, $dst">;
 def SUBXCCrr: F3_1<2, 0b011100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subxcc $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subxcc $b, $c, $dst">;
 def SUBXCCri: F3_2<2, 0b011100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subxcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subxcc $b, $c, $dst">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr  : F3_1<2, 0b001010, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "umul $b, $c, $dst">;
 def UMULri  : F3_2<2, 0b001010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umul">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "umul $b, $c, $dst">;
 def SMULrr  : F3_1<2, 0b001011, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "smul $b, $c, $dst">;
 def SMULri  : F3_2<2, 0b001011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smul">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "smul $b, $c, $dst">;
 def UMULCCrr: F3_1<2, 0b011010, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "umulcc $b, $c, $dst">;
 def UMULCCri: F3_2<2, 0b011010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umulcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "umulcc $b, $c, $dst">;
 def SMULCCrr: F3_1<2, 0b011011, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "smulcc $b, $c, $dst">;
 def SMULCCri: F3_2<2, 0b011011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smulcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "smulcc $b, $c, $dst">;
 
 // Section B.19 - Divide Instructions, p. 115
 def UDIVrr   : F3_1<2, 0b001110, 
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "udiv $b, $c, $dst">;
 def UDIVri   : F3_2<2, 0b001110,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udiv">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "udiv $b, $c, $dst">;
 def SDIVrr   : F3_1<2, 0b001111,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "sdiv $b, $c, $dst">;
 def SDIVri   : F3_2<2, 0b001111,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdiv">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "sdiv $b, $c, $dst">;
 def UDIVCCrr : F3_1<2, 0b011110,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "udivcc $b, $c, $dst">;
 def UDIVCCri : F3_2<2, 0b011110,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udivcc">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "udivcc $b, $c, $dst">;
 def SDIVCCrr : F3_1<2, 0b011111,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "sdivcc $b, $c, $dst">;
 def SDIVCCri : F3_2<2, 0b011111,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdivcc">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "sdivcc $b, $c, $dst">;
 
 // Section B.20 - SAVE and RESTORE, p. 117
 def SAVErr    : F3_1<2, 0b111100,
                      (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                      "save $b, $c, $dst">;
 def SAVEri    : F3_2<2, 0b111100,
-                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "save">;
+                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                     "save $b, $c, $dst">;
 def RESTORErr : F3_1<2, 0b111101,
                      (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                      "restore $b, $c, $dst">;
 def RESTOREri : F3_2<2, 0b111101,
-                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "restore">;
+                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                     "restore $b, $c, $dst">;
 
 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
 
@@ -391,7 +443,8 @@ def WRrr : F3_1<2, 0b110000,
                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                 "wr $b, $c, $dst">;
 def WRri : F3_2<2, 0b110000,
-                (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "wr">;                    // wr rs1, imm, rd
+                (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                "wr $b, $c, $dst">;
 
 // Convert Integer to Floating-point Instructions, p. 141
 def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
diff --git a/lib/Target/SparcV8/SparcV8AsmPrinter.cpp b/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
index cedbe3fed09..8867275d619 100644
--- a/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
+++ b/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
@@ -422,40 +422,6 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
   if (CloseParen) O << ")";
 }
 
-static bool isLoadInstruction (const MachineInstr *MI) {
-  switch (MI->getOpcode ()) {
-  case V8::LDSB:
-  case V8::LDSH:
-  case V8::LDUB:
-  case V8::LDUH:
-  case V8::LD:
-  case V8::LDD:
-  case V8::LDFrr:
-  case V8::LDFri:
-  case V8::LDDFrr:
-  case V8::LDDFri:
-    return true;
-  default:
-    return false;
-  }
-}
-
-static bool isStoreInstruction (const MachineInstr *MI) {
-  switch (MI->getOpcode ()) {
-  case V8::STB:
-  case V8::STH:
-  case V8::ST:
-  case V8::STD:
-  case V8::STFrr:
-  case V8::STFri:
-  case V8::STDFrr:
-  case V8::STDFri:
-    return true;
-  default:
-    return false;
-  }
-}
-
 static bool isPseudoInstruction (const MachineInstr *MI) {
   switch (MI->getOpcode ()) {
   case V8::PHI:
@@ -507,23 +473,6 @@ void SparcV8AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
 
   O << Desc.Name << " ";
 
-  // Printing memory instructions is a special case.
-  // for loads:  %dest = op %base, offset --> op [%base + offset], %dest
-  // for stores: op %base, offset, %src   --> op %src, [%base + offset]
-  if (isLoadInstruction (MI)) {
-    printBaseOffsetPair (MI, 1);
-    O << ", ";
-    printOperand (MI, 0);
-    O << "\n";
-    return;
-  } else if (isStoreInstruction (MI)) {
-    printOperand (MI, 2);
-    O << ", ";
-    printBaseOffsetPair (MI, 0);
-    O << "\n";
-    return;
-  }
-
   // print non-immediate, non-register-def operands
   // then print immediate operands
   // then print register-def operands.
diff --git a/lib/Target/SparcV8/SparcV8InstrFormats.td b/lib/Target/SparcV8/SparcV8InstrFormats.td
index b63e39148fb..e30edce83c7 100644
--- a/lib/Target/SparcV8/SparcV8InstrFormats.td
+++ b/lib/Target/SparcV8/SparcV8InstrFormats.td
@@ -73,14 +73,14 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
   let Inst{4-0}  = rs2;
 }
 
-class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
+class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
   bits<13> simm13;
 
   dag OperandList = ops;
+  let AsmString   = asmstr;
   
   let op         = opVal;
   let op3        = op3val;
-  let Name       = name;
 
   let Inst{13}   = 1;     // i field = 1
   let Inst{12-0} = simm13;
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 9cb9811dc5b..6bf5f27d18c 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -51,80 +51,99 @@ def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
   let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
     def RET : F3_2<2, 0b111000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ret">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "ret $b, $c, $dst">;
   let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
-    def RETL: F3_2<2, 0b111000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "retl">;
+    def RETL: F3_2<2, 0b111000, (ops),
+                   "retl">;
 }
 // CMP is a special case of SUBCC where destination is ignored, by setting it to
 // %g0 (hardwired zero).
 // FIXME: should keep track of the fact that it defs the integer condition codes
 let rd = 0 in
   def CMPri: F3_2<2, 0b010100,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "cmp">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "cmp $b, $c, $dst">;
 
 // Section B.1 - Load Integer Instructions, p. 90
 def LDSB: F3_2<3, 0b001001,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsb">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldsb [$b+$c], $dst">;
 def LDSH: F3_2<3, 0b001010,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsh">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldsh [$b+$c], $dst">;
 def LDUB: F3_2<3, 0b000001,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldub">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldub [$b+$c], $dst">;
 def LDUH: F3_2<3, 0b000010,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "lduh">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "lduh [$b+$c], $dst">;
 def LD  : F3_2<3, 0b000000,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ld [$b+$c], $dst">;
 def LDD : F3_2<3, 0b000011,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">;
+               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+               "ldd [$b+$c], $dst">;
 
 // Section B.2 - Load Floating-point Instructions, p. 92
 def LDFrr  : F3_1<3, 0b100000,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ld $b, $c, $dst">;
+                  "ld [$b+$c], $dst">;
 def LDFri  : F3_2<3, 0b100000,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ld [$b+$c], $dst">;
 def LDDFrr : F3_1<3, 0b100011,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ldd $b, $c, $dst">;
+                  "ldd [$b+$c], $dst">;
 def LDDFri : F3_2<3, 0b100011,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ldd [$b+$c], $dst">;
 def LDFSRrr: F3_1<3, 0b100001,
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "ld $b, $c, $dst">;
+                  "ld [$b+$c], $dst">;
 def LDFSRri: F3_2<3, 0b100001,
-                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">;
+                  (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                  "ld [$b+$c], $dst">;
 
 // Section B.4 - Store Integer Instructions, p. 95
 def STB : F3_2<3, 0b000101,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "stb">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "stb $src, [$base+$offset]">;
 def STH : F3_2<3, 0b000110,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sth">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "sth $src, [$base+$offset]">;
 def ST  : F3_2<3, 0b000100,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "st $src, [$base+$offset]">;
 def STD : F3_2<3, 0b000111,
-               (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+               (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+               "std $src, [$base+$offset]">;
 
 // Section B.5 - Store Floating-point Instructions, p. 97
 def STFrr   : F3_1<3, 0b100100,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "st $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "st $src, [$base+$offset]">;
 def STFri   : F3_2<3, 0b100100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "st $src, [$base+$offset]">;
 def STDFrr  : F3_1<3, 0b100111,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "std $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "std  $src, [$base+$offset]">;
 def STDFri  : F3_2<3, 0b100111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "std $src, [$base+$offset]">;
 def STFSRrr : F3_1<3, 0b100101,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "st $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "st $src, [$base+$offset]">;
 def STFSRri : F3_2<3, 0b100101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "st $src, [$base+$offset]">;
 def STDFQrr : F3_1<3, 0b100110,
-                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "std $b, $c, $dst">;
+                   (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
+                   "std $src, [$base+$offset]">;
 def STDFQri : F3_2<3, 0b100110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">;
+                   (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
+                   "std $src, [$base+$offset]">;
 
 // Section B.9 - SETHI Instruction, p. 104
 def SETHIi: F2_1<0b100, "sethi">;
@@ -139,179 +158,212 @@ def ANDrr   : F3_1<2, 0b000001,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "and $b, $c, $dst">;
 def ANDri   : F3_2<2, 0b000001,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "and">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "and $b, $c, $dst">;
 def ANDCCrr : F3_1<2, 0b010001,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andcc $b, $c, $dst">;
 def ANDCCri : F3_2<2, 0b010001,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andcc $b, $c, $dst">;
 def ANDNrr  : F3_1<2, 0b000101,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andn $b, $c, $dst">;
 def ANDNri  : F3_2<2, 0b000101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andn">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andn $b, $c, $dst">;
 def ANDNCCrr: F3_1<2, 0b010101,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "andncc $b, $c, $dst">;
 def ANDNCCri: F3_2<2, 0b010101,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andncc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "andncc $b, $c, $dst">;
 def ORrr    : F3_1<2, 0b000010,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "or $b, $c, $dst">;
 def ORri    : F3_2<2, 0b000010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "or">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "or $b, $c, $dst">;
 def ORCCrr  : F3_1<2, 0b010010,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orcc $b, $c, $dst">;
 def ORCCri  : F3_2<2, 0b010010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orcc $b, $c, $dst">;
 def ORNrr   : F3_1<2, 0b000110,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orn $b, $c, $dst">;
 def ORNri   : F3_2<2, 0b000110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orn">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orn $b, $c, $dst">;
 def ORNCCrr : F3_1<2, 0b010110,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "orncc $b, $c, $dst">;
 def ORNCCri : F3_2<2, 0b010110,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orncc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "orncc $b, $c, $dst">;
 def XORrr   : F3_1<2, 0b000011,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xor $b, $c, $dst">;
 def XORri   : F3_2<2, 0b000011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xor">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xor $b, $c, $dst">;
 def XORCCrr : F3_1<2, 0b010011,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xorcc $b, $c, $dst">;
 def XORCCri : F3_2<2, 0b010011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xorcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xorcc $b, $c, $dst">;
 def XNORrr  : F3_1<2, 0b000111,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xnor $b, $c, $dst">;
 def XNORri  : F3_2<2, 0b000111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnor">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xnor $b, $c, $dst">;
 def XNORCCrr: F3_1<2, 0b010111,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xnorcc $b, $c, $dst">;
 def XNORCCri: F3_2<2, 0b010111,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnorcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "xnorcc $b, $c, $dst">;
 
 // Section B.12 - Shift Instructions, p. 107
 def SLLrr : F3_1<2, 0b100101,
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                  "sll $b, $c, $dst">;
 def SLLri : F3_2<2, 0b100101,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sll">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "sll $b, $c, $dst">;
 def SRLrr : F3_1<2, 0b100110, 
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "srl $b, $c, $dst">;
 def SRLri : F3_2<2, 0b100110,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "srl">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "srl $b, $c, $dst">;
 def SRArr : F3_1<2, 0b100111, 
                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "sra $b, $c, $dst">;
 def SRAri : F3_2<2, 0b100111,
-                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sra">;
+                 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                 "sla $b, $c, $dst">;
 
 // Section B.13 - Add Instructions, p. 108
 def ADDrr   : F3_1<2, 0b000000, 
                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                   "add $b, $c, $dst">;
 def ADDri   : F3_2<2, 0b000000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "add">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "add $b, $c, $dst">;
 def ADDCCrr : F3_1<2, 0b010000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addcc $b, $c, $dst">;
 def ADDCCri : F3_2<2, 0b010000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addcc $b, $c, $dst">;
 def ADDXrr  : F3_1<2, 0b001000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addx $b, $c, $dst">;
 def ADDXri  : F3_2<2, 0b001000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addx">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addx $b, $c, $dst">;
 def ADDXCCrr: F3_1<2, 0b011000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "addxcc $b, $c, $dst">;
 def ADDXCCri: F3_2<2, 0b011000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addxcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "addxcc $b, $c, $dst">;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, 
-                  (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "sub $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "sub $b, $c, $dst">;
 def SUBri   : F3_2<2, 0b000100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sub">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "sub $b, $c, $dst">;
 def SUBCCrr : F3_1<2, 0b010100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subcc $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subcc $b, $c, $dst">;
 def SUBCCri : F3_2<2, 0b010100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subcc $b, $c, $dst">;
 def SUBXrr  : F3_1<2, 0b001100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subx $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subx $b, $c, $dst">;
 def SUBXri  : F3_2<2, 0b001100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subx">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subx $b, $c, $dst">;
 def SUBXCCrr: F3_1<2, 0b011100, 
-                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                  "subxcc $b, $c, $dst">;
+                   (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+                   "subxcc $b, $c, $dst">;
 def SUBXCCri: F3_2<2, 0b011100,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subxcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "subxcc $b, $c, $dst">;
 
 // Section B.18 - Multiply Instructions, p. 113
 def UMULrr  : F3_1<2, 0b001010, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "umul $b, $c, $dst">;
 def UMULri  : F3_2<2, 0b001010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umul">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "umul $b, $c, $dst">;
 def SMULrr  : F3_1<2, 0b001011, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "smul $b, $c, $dst">;
 def SMULri  : F3_2<2, 0b001011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smul">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "smul $b, $c, $dst">;
 def UMULCCrr: F3_1<2, 0b011010, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "umulcc $b, $c, $dst">;
 def UMULCCri: F3_2<2, 0b011010,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umulcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "umulcc $b, $c, $dst">;
 def SMULCCrr: F3_1<2, 0b011011, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "smulcc $b, $c, $dst">;
 def SMULCCri: F3_2<2, 0b011011,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smulcc">;
+                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                   "smulcc $b, $c, $dst">;
 
 // Section B.19 - Divide Instructions, p. 115
 def UDIVrr   : F3_1<2, 0b001110, 
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "udiv $b, $c, $dst">;
 def UDIVri   : F3_2<2, 0b001110,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udiv">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "udiv $b, $c, $dst">;
 def SDIVrr   : F3_1<2, 0b001111,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "sdiv $b, $c, $dst">;
 def SDIVri   : F3_2<2, 0b001111,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdiv">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "sdiv $b, $c, $dst">;
 def UDIVCCrr : F3_1<2, 0b011110,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "udivcc $b, $c, $dst">;
 def UDIVCCri : F3_2<2, 0b011110,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udivcc">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "udivcc $b, $c, $dst">;
 def SDIVCCrr : F3_1<2, 0b011111,
                     (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                     "sdivcc $b, $c, $dst">;
 def SDIVCCri : F3_2<2, 0b011111,
-                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdivcc">;
+                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                    "sdivcc $b, $c, $dst">;
 
 // Section B.20 - SAVE and RESTORE, p. 117
 def SAVErr    : F3_1<2, 0b111100,
                      (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                      "save $b, $c, $dst">;
 def SAVEri    : F3_2<2, 0b111100,
-                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "save">;
+                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                     "save $b, $c, $dst">;
 def RESTORErr : F3_1<2, 0b111101,
                      (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                      "restore $b, $c, $dst">;
 def RESTOREri : F3_2<2, 0b111101,
-                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "restore">;
+                     (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                     "restore $b, $c, $dst">;
 
 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
 
@@ -391,7 +443,8 @@ def WRrr : F3_1<2, 0b110000,
                 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                 "wr $b, $c, $dst">;
 def WRri : F3_2<2, 0b110000,
-                (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "wr">;                    // wr rs1, imm, rd
+                (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+                "wr $b, $c, $dst">;
 
 // Convert Integer to Floating-point Instructions, p. 141
 def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;