6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-20 14:29:27 +00:00
Code Issues Projects Releases Wiki Activity

Fix encoding of Ra register for ARM smla* instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-11 01:27:41 +00:00
parent 336b8b4244
commit d507d1f616
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2533,7 +2533,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
multiclass AI_smla<string opc, PatFrag opnode> { multiclass AI_smla<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd), def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, [(set GPR:$Rd, (add GPR:$Ra,
@ -2541,35 +2541,35 @@ multiclass AI_smla<string opc, PatFrag opnode> {
(sext_inreg GPR:$Rm, i16))))]>, (sext_inreg GPR:$Rm, i16))))]>,
Requires<[IsARM, HasV5TE]>; Requires<[IsARM, HasV5TE]>;
def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd), def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16), [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
(sra GPR:$Rm, (i32 16)))))]>, (sra GPR:$Rm, (i32 16)))))]>,
Requires<[IsARM, HasV5TE]>; Requires<[IsARM, HasV5TE]>;
def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd), def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
(sext_inreg GPR:$Rm, i16))))]>, (sext_inreg GPR:$Rm, i16))))]>,
Requires<[IsARM, HasV5TE]>; Requires<[IsARM, HasV5TE]>;
def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd), def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
(sra GPR:$Rm, (i32 16)))))]>, (sra GPR:$Rm, (i32 16)))))]>,
Requires<[IsARM, HasV5TE]>; Requires<[IsARM, HasV5TE]>;
def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd), def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
(sext_inreg GPR:$Rm, i16)), (i32 16))))]>, (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
Requires<[IsARM, HasV5TE]>; Requires<[IsARM, HasV5TE]>;
def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd), def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,