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[mips] [IAS] Add support for expanding LASym with a source register operand.

Browse Source 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9348

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239910 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-06-17 14:31:51 +00:00
parent 4dd3b87048
commit d510c1085a
2 changed files with 25 additions and 12 deletions
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31
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -186,9 +186,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
bool Is32BitSym, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
@ -1929,18 +1929,20 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind");
const MCOperand &ImmOp = Inst.getOperand(2);
assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind");
if (!ImmOp.isImm()) {
if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
Instructions))
if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(),
SrcRegOp.getReg(), Is32BitImm, IDLoc,
Instructions))
return true;
return false;
}
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind");
if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
Is32BitImm, IDLoc, Instructions))
@ -1959,8 +1961,9 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind");
if (!ImmOp.isImm()) {
if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
Instructions))
if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(),
Mips::NoRegister, Is32BitImm, IDLoc,
Instructions))
return true;
return false;
@ -1973,9 +1976,9 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
return false;
}
bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
bool Is32BitSym, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::loadAndAddSymbolAddress(
const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym,
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
warnIfNoMacro(IDLoc);
if (Is32BitSym && isABI_N64())
@ -2024,6 +2027,10 @@ bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
Instructions);
}
if (SrcReg != Mips::NoRegister)
createAddu(DstReg, DstReg, SrcReg, Instructions);
return false;
}

6
test/MC/Mips/mips-expansions.s
View File

@ -43,6 +43,12 @@
# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
la $8, symbol($9)
# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
# CHECK: addu $8, $8, $9 # encoding: [0x21,0x40,0x09,0x01]
# LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
.set noat