From d5275157b540f53fe3795489229c021390e90b3f Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Fri, 17 Nov 2006 23:53:28 +0000
Subject: [PATCH] add encoding for BCC, after finally wrestling strange
 ppc/tblgen endianness issues to the ground.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31836 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCInstrFormats.td | 18 ++++++++++++++++++
 lib/Target/PowerPC/PPCInstrInfo.td    |  7 ++++---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index ce86d8f358b..abf2267f06b 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -74,6 +74,24 @@ class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
   let Inst{31}    = lk;
 }
 
+class CBForm<bits<6> opcode, bit aa, bit lk, dag OL, 
+             string asmstr> : I<opcode, OL, asmstr, BrB> {
+  bits<7> BIBO;  // 2 bits of BI and 5 bits of BO.
+  bits<3>  CR;
+  bits<14> BD;
+
+  bits<5> BI;
+  let BI{0-1} = BIBO{5-6};
+  let BI{2-4} = CR{0-2};
+
+  let Inst{6-10}  = BIBO{4-0};
+  let Inst{11-15} = BI;
+  let Inst{16-29} = BD;
+  let Inst{30}    = aa;
+  let Inst{31}    = lk;
+}
+
+
 // 1.7.4 D-Form
 class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
                  list<dag> pattern> 
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 1015b7e7de0..70a871b6e01 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -361,10 +361,11 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
   // BCC represents an arbitrary conditional branch on a predicate.
   // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
   // a two-value operand where a dag node expects two operands. :( 
-  def BCC : Pseudo<(ops pred:$cond, target:$dst),
-                   "b${cond:cc} ${cond:reg}, $dst",
-                   [/*(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)*/]>;
+  def BCC : CBForm<16, 0, 0, (ops pred:$cond, target:$dst),
+                   "b${cond:cc} ${cond:reg}, $dst"
+                   /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
 
+// REMOVE BForm when these go away.
   def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
                   "blt $crS, $block", BrB>;
   def BLE : BForm<16, 0, 0, 4,  1, (ops CRRC:$crS, target:$block),