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[X86] Fix some cases where some 8-bit instructions were marked as being convertible to three address instructions, but aren't really.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224940 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -999,12 +999,13 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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bit CommutableRR, bit ConvertibleToThreeAddress> {
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = CommutableRR,
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isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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let isCommutable = CommutableRR in {
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def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
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def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
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def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
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def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
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def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
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def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
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} // isConvertibleToThreeAddress
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} // isCommutable
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def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
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@ -1017,6 +1018,8 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
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def NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
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def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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@ -1024,7 +1027,6 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
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def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
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def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
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def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
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def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
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def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
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@ -1080,12 +1082,13 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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bit ConvertibleToThreeAddress> {
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let Uses = [EFLAGS], Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = CommutableRR,
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isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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let isCommutable = CommutableRR in {
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def NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>;
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def NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>;
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def NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>;
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def NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>;
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def NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>;
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def NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>;
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} // isConvertibleToThreeAddress
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} // isCommutable
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def NAME#8rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi8>;
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@ -1098,6 +1101,8 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>;
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def NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>;
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def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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@ -1105,7 +1110,6 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;
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def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;
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def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;
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def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>;
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@ -1158,12 +1162,13 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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SDNode opnode,
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bit CommutableRR, bit ConvertibleToThreeAddress> {
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let Defs = [EFLAGS] in {
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let isCommutable = CommutableRR,
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isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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let isCommutable = CommutableRR in {
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def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
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def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
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def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
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def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
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def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
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def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
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}
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} // isCommutable
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def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
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@ -1176,6 +1181,8 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
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def NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
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def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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// NOTE: These are order specific, we want the ri8 forms to be listed
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// first so that they are slightly preferred to the ri forms.
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@ -1183,7 +1190,6 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
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def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
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def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
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def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
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def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
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def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
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