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Use range-based for loops. NFC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-12-09 08:05:51 +00:00
parent ff3745b4ff
commit d5578c8ba3
2 changed files with 24 additions and 35 deletions
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44
utils/TableGen/CodeGenSchedule.cpp
View File

@ -74,11 +74,10 @@ struct InstRegexOp : public SetTheory::Operator {
}
RegexList.push_back(Regex(pat));
}
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I) {
for (const CodeGenInstruction *Inst : Target.instructions()) {
for (auto &R : RegexList) {
if (R.match((*I)->TheDef->getName()))
Elts.insert((*I)->TheDef);
if (R.match(Inst->TheDef->getName()))
Elts.insert(Inst->TheDef);
}
}
}
@ -214,9 +213,8 @@ void CodeGenSchedModels::collectSchedRW() {
// Find all SchedReadWrites referenced by instruction defs.
RecVec SWDefs, SRDefs;
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I) {
Record *SchedDef = (*I)->TheDef;
for (const CodeGenInstruction *Inst : Target.instructions()) {
Record *SchedDef = Inst->TheDef;
if (SchedDef->isValueUnset("SchedRW"))
continue;
RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
@ -509,18 +507,17 @@ void CodeGenSchedModels::collectSchedClasses() {
// Create a SchedClass for each unique combination of itinerary class and
// SchedRW list.
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I) {
Record *ItinDef = (*I)->TheDef->getValueAsDef("Itinerary");
for (const CodeGenInstruction *Inst : Target.instructions()) {
Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
IdxVec Writes, Reads;
if (!(*I)->TheDef->isValueUnset("SchedRW"))
findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
if (!Inst->TheDef->isValueUnset("SchedRW"))
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
// ProcIdx == 0 indicates the class applies to all processors.
IdxVec ProcIndices(1, 0);
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
InstrClassMap[(*I)->TheDef] = SCIdx;
InstrClassMap[Inst->TheDef] = SCIdx;
}
// Create classes for InstRW defs.
RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
@ -535,18 +532,16 @@ void CodeGenSchedModels::collectSchedClasses() {
if (!EnableDump)
return;
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I) {
std::string InstName = (*I)->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup((*I)->TheDef);
for (const CodeGenInstruction *Inst : Target.instructions()) {
std::string InstName = Inst->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
if (!SCIdx) {
dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n';
dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
continue;
}
CodeGenSchedClass &SC = getSchedClass(SCIdx);
if (SC.ProcIndices[0] != 0)
PrintFatalError((*I)->TheDef->getLoc(), "Instruction's sched class "
PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
"must not be subtarget specific.");
IdxVec ProcIndices;
@ -584,7 +579,7 @@ void CodeGenSchedModels::collectSchedClasses() {
for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
PE = ProcModels.end(); PI != PE; ++PI) {
if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
dbgs() << "No machine model for " << (*I)->TheDef->getName()
dbgs() << "No machine model for " << Inst->TheDef->getName()
<< " on processor " << PI->ModelName << '\n';
}
}
@ -781,9 +776,7 @@ bool CodeGenSchedModels::hasItineraries() const {
// Gather the processor itineraries.
void CodeGenSchedModels::collectProcItins() {
for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
PE = ProcModels.end(); PI != PE; ++PI) {
CodeGenProcModel &ProcModel = *PI;
for (CodeGenProcModel &ProcModel : ProcModels) {
if (!ProcModel.hasItineraries())
continue;
@ -1502,8 +1495,7 @@ void CodeGenSchedModels::collectProcResources() {
PM.ProcResourceDefs.push_back(*RI);
}
// Finalize each ProcModel by sorting the record arrays.
for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
CodeGenProcModel &PM = ProcModels[PIdx];
for (CodeGenProcModel &PM : ProcModels) {
std::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(),
LessRecord());
std::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(),

15
utils/TableGen/CodeGenTarget.cpp
View File

@ -151,11 +151,11 @@ const std::string &CodeGenTarget::getName() const {
}
std::string CodeGenTarget::getInstNamespace() const {
for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
for (const CodeGenInstruction *Inst : instructions()) {
// Make sure not to pick up "TargetOpcode" by accidentally getting
// the namespace off the PHI instruction or something.
if ((*i)->Namespace != "TargetOpcode")
return (*i)->Namespace;
if (Inst->Namespace != "TargetOpcode")
return Inst->Namespace;
}
return "";
@ -307,9 +307,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
}
unsigned EndOfPredefines = InstrsByEnum.size();
for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
I = Insts.begin(), E = Insts.end(); I != E; ++I) {
const CodeGenInstruction *CGI = I->second;
for (const auto &I : Insts) {
const CodeGenInstruction *CGI = I.second;
if (CGI->Namespace != "TargetOpcode")
InstrsByEnum.push_back(CGI);
}
@ -339,9 +338,7 @@ void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
return;
std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
I != E; ++I) {
Record *R = *I;
for (Record *R : Insts) {
if (R->getValueAsString("Namespace") == "TargetOpcode" ||
R->getValueAsBit("isPseudo"))
continue;