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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
Use range-based for loops. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223762 91177308-0d34-0410-b5e6-96231b3b80d8
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ff3745b4ff
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@ -74,11 +74,10 @@ struct InstRegexOp : public SetTheory::Operator {
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}
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}
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RegexList.push_back(Regex(pat));
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RegexList.push_back(Regex(pat));
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}
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}
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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E = Target.inst_end(); I != E; ++I) {
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for (auto &R : RegexList) {
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for (auto &R : RegexList) {
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if (R.match((*I)->TheDef->getName()))
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if (R.match(Inst->TheDef->getName()))
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Elts.insert((*I)->TheDef);
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Elts.insert(Inst->TheDef);
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}
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}
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}
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}
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}
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}
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@ -214,9 +213,8 @@ void CodeGenSchedModels::collectSchedRW() {
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// Find all SchedReadWrites referenced by instruction defs.
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// Find all SchedReadWrites referenced by instruction defs.
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RecVec SWDefs, SRDefs;
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RecVec SWDefs, SRDefs;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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E = Target.inst_end(); I != E; ++I) {
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Record *SchedDef = Inst->TheDef;
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Record *SchedDef = (*I)->TheDef;
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if (SchedDef->isValueUnset("SchedRW"))
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if (SchedDef->isValueUnset("SchedRW"))
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continue;
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continue;
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RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
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RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
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@ -509,18 +507,17 @@ void CodeGenSchedModels::collectSchedClasses() {
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// Create a SchedClass for each unique combination of itinerary class and
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// Create a SchedClass for each unique combination of itinerary class and
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// SchedRW list.
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// SchedRW list.
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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E = Target.inst_end(); I != E; ++I) {
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Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
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Record *ItinDef = (*I)->TheDef->getValueAsDef("Itinerary");
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IdxVec Writes, Reads;
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IdxVec Writes, Reads;
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if (!(*I)->TheDef->isValueUnset("SchedRW"))
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if (!Inst->TheDef->isValueUnset("SchedRW"))
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findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
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findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
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// ProcIdx == 0 indicates the class applies to all processors.
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// ProcIdx == 0 indicates the class applies to all processors.
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IdxVec ProcIndices(1, 0);
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IdxVec ProcIndices(1, 0);
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unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
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unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
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InstrClassMap[(*I)->TheDef] = SCIdx;
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InstrClassMap[Inst->TheDef] = SCIdx;
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}
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}
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// Create classes for InstRW defs.
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// Create classes for InstRW defs.
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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@ -535,18 +532,16 @@ void CodeGenSchedModels::collectSchedClasses() {
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if (!EnableDump)
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if (!EnableDump)
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return;
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return;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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E = Target.inst_end(); I != E; ++I) {
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std::string InstName = Inst->TheDef->getName();
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unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
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std::string InstName = (*I)->TheDef->getName();
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unsigned SCIdx = InstrClassMap.lookup((*I)->TheDef);
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if (!SCIdx) {
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if (!SCIdx) {
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dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n';
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dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
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continue;
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continue;
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}
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}
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CodeGenSchedClass &SC = getSchedClass(SCIdx);
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CodeGenSchedClass &SC = getSchedClass(SCIdx);
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if (SC.ProcIndices[0] != 0)
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if (SC.ProcIndices[0] != 0)
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PrintFatalError((*I)->TheDef->getLoc(), "Instruction's sched class "
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PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
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"must not be subtarget specific.");
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"must not be subtarget specific.");
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IdxVec ProcIndices;
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IdxVec ProcIndices;
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@ -584,7 +579,7 @@ void CodeGenSchedModels::collectSchedClasses() {
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for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
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for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
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PE = ProcModels.end(); PI != PE; ++PI) {
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PE = ProcModels.end(); PI != PE; ++PI) {
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if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
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if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
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dbgs() << "No machine model for " << (*I)->TheDef->getName()
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dbgs() << "No machine model for " << Inst->TheDef->getName()
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<< " on processor " << PI->ModelName << '\n';
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<< " on processor " << PI->ModelName << '\n';
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}
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}
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}
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}
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@ -781,9 +776,7 @@ bool CodeGenSchedModels::hasItineraries() const {
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// Gather the processor itineraries.
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// Gather the processor itineraries.
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void CodeGenSchedModels::collectProcItins() {
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void CodeGenSchedModels::collectProcItins() {
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for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
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for (CodeGenProcModel &ProcModel : ProcModels) {
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PE = ProcModels.end(); PI != PE; ++PI) {
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CodeGenProcModel &ProcModel = *PI;
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if (!ProcModel.hasItineraries())
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if (!ProcModel.hasItineraries())
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continue;
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continue;
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@ -1502,8 +1495,7 @@ void CodeGenSchedModels::collectProcResources() {
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PM.ProcResourceDefs.push_back(*RI);
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PM.ProcResourceDefs.push_back(*RI);
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}
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}
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// Finalize each ProcModel by sorting the record arrays.
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// Finalize each ProcModel by sorting the record arrays.
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for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
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for (CodeGenProcModel &PM : ProcModels) {
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CodeGenProcModel &PM = ProcModels[PIdx];
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std::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(),
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std::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(),
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LessRecord());
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LessRecord());
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std::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(),
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std::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(),
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@ -151,11 +151,11 @@ const std::string &CodeGenTarget::getName() const {
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}
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}
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std::string CodeGenTarget::getInstNamespace() const {
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std::string CodeGenTarget::getInstNamespace() const {
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for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
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for (const CodeGenInstruction *Inst : instructions()) {
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// the namespace off the PHI instruction or something.
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// the namespace off the PHI instruction or something.
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if ((*i)->Namespace != "TargetOpcode")
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if (Inst->Namespace != "TargetOpcode")
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return (*i)->Namespace;
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return Inst->Namespace;
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}
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}
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return "";
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return "";
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@ -307,9 +307,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
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}
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}
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unsigned EndOfPredefines = InstrsByEnum.size();
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unsigned EndOfPredefines = InstrsByEnum.size();
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for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
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for (const auto &I : Insts) {
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I = Insts.begin(), E = Insts.end(); I != E; ++I) {
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const CodeGenInstruction *CGI = I.second;
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const CodeGenInstruction *CGI = I->second;
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if (CGI->Namespace != "TargetOpcode")
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if (CGI->Namespace != "TargetOpcode")
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InstrsByEnum.push_back(CGI);
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InstrsByEnum.push_back(CGI);
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}
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}
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@ -339,9 +338,7 @@ void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
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return;
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return;
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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for (Record *R : Insts) {
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I != E; ++I) {
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Record *R = *I;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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R->getValueAsBit("isPseudo"))
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continue;
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continue;
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