mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
* Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack. * Added support for X86 SETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
87bddeb2af
commit
d5781fca4f
@ -1621,6 +1621,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Node->getOperand(2));
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break;
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}
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case TargetLowering::Custom: {
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SDOperand Tmp =
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TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
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Tmp1, Tmp2, Node->getOperand(2)), DAG);
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if (Tmp.Val) {
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Result = LegalizeOp(Tmp);
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break;
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}
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// FALLTHROUGH if the target thinks it is legal.
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}
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case TargetLowering::Legal:
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if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
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Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
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@ -119,6 +119,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (X86DAGIsel) {
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setOperationAction(ISD::SELECT , MVT::i16 , Custom);
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setOperationAction(ISD::SELECT , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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}
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// We don't have line number support yet.
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@ -256,7 +259,10 @@ SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
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}
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break;
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}
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return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
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Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
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Copy.getValue(1));
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}
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//===----------------------------------------------------------------------===//
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@ -999,10 +1005,20 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Tys.push_back(MVT::Other);
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return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
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}
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case ISD::SETCC: {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDOperand CC = Op.getOperand(2);
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SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Op.getOperand(0), Op.getOperand(1));
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return DAG.getNode(X86ISD::SETCC, MVT::i8, CC, Cond);
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}
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case ISD::SELECT: {
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SDOperand Cond = Op.getOperand(0);
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SDOperand CC;
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if (Cond.getOpcode() == ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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} else if (Cond.getOpcode() == ISD::SETCC) {
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CC = Cond.getOperand(2);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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@ -1014,12 +1030,14 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Op.getOperand(1), Op.getOperand(2), CC, Cond);
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}
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case ISD::BRCOND: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand Cond = Op.getOperand(1);
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SDOperand Dest = Op.getOperand(2);
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SDOperand CC;
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// TODO: handle Cond == OR / AND / XOR
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if (Cond.getOpcode() == ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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} else if (Cond.getOpcode() == ISD::SETCC) {
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CC = Cond.getOperand(2);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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@ -1061,6 +1079,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::TEST: return "X86ISD::TEST";
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case X86ISD::SETCC: return "X86ISD::SETCC";
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case X86ISD::CMOV: return "X86ISD::CMOV";
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case X86ISD::BRCOND: return "X86ISD::BRCOND";
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case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
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@ -81,13 +81,24 @@ namespace llvm {
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/// X86 compare and logical compare instructions.
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CMP, TEST,
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/// X86 conditional moves.
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// X86 conditional moves. Operand 1 and operand 2 are the two values
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/// to select from (operand 1 is a R/W operand). Operand 3 is the condition
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/// code, and operand 4 is the flag operand produced by a CMP or TEST
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/// instruction.
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CMOV,
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/// X86 conditional branches.
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/// X86 conditional branches. Operand 1 is the chain operand, operand 2
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/// is the block to branch if condition is true, operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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// Return with a flag operand.
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/// Return with a flag operand. Operand 1 is the number of bytes of stack
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/// to pop, operand 2 is the chain and operand 3 is a flag operand.
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RET_FLAG,
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};
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}
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@ -28,25 +28,31 @@ def SDTX86BrCond : SDTypeProfile<0, 3,
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[SDTCisVT<0, OtherVT>,
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SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>;
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def SDTX86RetFlag : SDTypeProfile<0, 1, [SDTCisVT<0, FlagVT>]>;
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def SDTX86SetCC : SDTypeProfile<1, 2,
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[SDTCisVT<0, i8>, SDTCisVT<1, OtherVT>,
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SDTCisVT<2, FlagVT>]>;
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def SDTX86RetFlag : SDTypeProfile<0, 2, [SDTCisVT<0, i16>,
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SDTCisVT<1, FlagVT>]>;
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def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
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def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
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def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
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def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>;
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def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
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def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>;
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def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
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def X86SetCC : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>;
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def X86retflag: SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
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def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>;
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT",
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SDTX86FpSet, [SDNPHasChain]>;
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT",
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SDTX86FpSet, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// X86 Operand Definitions.
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@ -283,12 +289,13 @@ let isTerminator = 1 in
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//
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// Return instructions.
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
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def RET : I<0xC3, RawFrm, (ops), "ret", []>;
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
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def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
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def : Pat<(X86retflag FLAG), (RET)>;
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def : Pat<(X86retflag 0, FLAG), (RET)>;
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def : Pat<(X86retflag imm:$amt, FLAG), (RETI imm:$amt)>;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1 in
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@ -1800,42 +1807,87 @@ def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
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def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
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def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
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def SETBr : I<0x92, MRM0r,
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(ops R8 :$dst),
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"setb $dst", []>, TB; // R8 = < unsign
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def SETBm : I<0x92, MRM0m,
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(ops i8mem:$dst),
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"setb $dst", []>, TB; // [mem8] = < unsign
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def SETAEr : I<0x93, MRM0r,
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(ops R8 :$dst),
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"setae $dst", []>, TB; // R8 = >= unsign
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def SETAEm : I<0x93, MRM0m,
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(ops i8mem:$dst),
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"setae $dst", []>, TB; // [mem8] = >= unsign
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def SETEr : I<0x94, MRM0r,
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(ops R8 :$dst),
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"sete $dst", []>, TB; // R8 = ==
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"sete $dst", [(set R8:$dst, (X86SetCC SETEQ, STATUS))]>,
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TB; // R8 = ==
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def SETEm : I<0x94, MRM0m,
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(ops i8mem:$dst),
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"sete $dst", []>, TB; // [mem8] = ==
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"sete $dst", [(store (X86SetCC SETEQ, STATUS), addr:$dst)]>,
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TB; // [mem8] = ==
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def SETNEr : I<0x95, MRM0r,
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(ops R8 :$dst),
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"setne $dst", []>, TB; // R8 = !=
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"setne $dst", [(set R8:$dst, (X86SetCC SETNE, STATUS))]>,
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TB; // R8 = !=
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def SETNEm : I<0x95, MRM0m,
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(ops i8mem:$dst),
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"setne $dst", []>, TB; // [mem8] = !=
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"setne $dst", [(store (X86SetCC SETNE, STATUS), addr:$dst)]>,
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TB; // [mem8] = !=
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def SETLr : I<0x9C, MRM0r,
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(ops R8 :$dst),
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"setl $dst", [(set R8:$dst, (X86SetCC SETLT, STATUS))]>,
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TB; // R8 = < signed
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def SETLm : I<0x9C, MRM0m,
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(ops i8mem:$dst),
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"setl $dst", [(store (X86SetCC SETLT, STATUS), addr:$dst)]>,
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TB; // [mem8] = < signed
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def SETGEr : I<0x9D, MRM0r,
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(ops R8 :$dst),
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"setge $dst", [(set R8:$dst, (X86SetCC SETGE, STATUS))]>,
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TB; // R8 = >= signed
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def SETGEm : I<0x9D, MRM0m,
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(ops i8mem:$dst),
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"setge $dst", [(store (X86SetCC SETGE, STATUS), addr:$dst)]>,
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TB; // [mem8] = >= signed
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def SETLEr : I<0x9E, MRM0r,
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(ops R8 :$dst),
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"setle $dst", [(set R8:$dst, (X86SetCC SETLE, STATUS))]>,
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TB; // R8 = <= signed
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def SETLEm : I<0x9E, MRM0m,
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(ops i8mem:$dst),
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"setle $dst", [(store (X86SetCC SETLE, STATUS), addr:$dst)]>,
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TB; // [mem8] = <= signed
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def SETGr : I<0x9F, MRM0r,
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(ops R8 :$dst),
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"setg $dst", [(set R8:$dst, (X86SetCC SETGT, STATUS))]>,
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TB; // R8 = > signed
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def SETGm : I<0x9F, MRM0m,
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(ops i8mem:$dst),
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"setg $dst", [(store (X86SetCC SETGT, STATUS), addr:$dst)]>,
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TB; // [mem8] = > signed
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def SETBr : I<0x92, MRM0r,
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(ops R8 :$dst),
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"setb $dst", [(set R8:$dst, (X86SetCC SETULT, STATUS))]>,
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TB; // R8 = < unsign
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def SETBm : I<0x92, MRM0m,
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(ops i8mem:$dst),
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"setb $dst", [(store (X86SetCC SETULT, STATUS), addr:$dst)]>,
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TB; // [mem8] = < unsign
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def SETAEr : I<0x93, MRM0r,
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(ops R8 :$dst),
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"setae $dst", [(set R8:$dst, (X86SetCC SETUGE, STATUS))]>,
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TB; // R8 = >= unsign
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def SETAEm : I<0x93, MRM0m,
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(ops i8mem:$dst),
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"setae $dst", [(store (X86SetCC SETUGE, STATUS), addr:$dst)]>,
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TB; // [mem8] = >= unsign
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def SETBEr : I<0x96, MRM0r,
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(ops R8 :$dst),
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"setbe $dst", []>, TB; // R8 = <= unsign
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"setbe $dst", [(set R8:$dst, (X86SetCC SETULE, STATUS))]>,
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TB; // R8 = <= unsign
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def SETBEm : I<0x96, MRM0m,
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(ops i8mem:$dst),
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"setbe $dst", []>, TB; // [mem8] = <= unsign
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"setbe $dst", [(store (X86SetCC SETULE, STATUS), addr:$dst)]>,
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TB; // [mem8] = <= unsign
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def SETAr : I<0x97, MRM0r,
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(ops R8 :$dst),
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"seta $dst", []>, TB; // R8 = > signed
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"seta $dst", [(set R8:$dst, (X86SetCC SETUGT, STATUS))]>,
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TB; // R8 = > signed
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def SETAm : I<0x97, MRM0m,
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(ops i8mem:$dst),
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"seta $dst", []>, TB; // [mem8] = > signed
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"seta $dst", [(store (X86SetCC SETUGT, STATUS), addr:$dst)]>,
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TB; // [mem8] = > signed
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def SETSr : I<0x98, MRM0r,
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(ops R8 :$dst),
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"sets $dst", []>, TB; // R8 = <sign bit>
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@ -1860,30 +1912,6 @@ def SETNPr : I<0x9B, MRM0r,
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def SETNPm : I<0x9B, MRM0m,
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(ops i8mem:$dst),
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"setnp $dst", []>, TB; // [mem8] = not parity
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def SETLr : I<0x9C, MRM0r,
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(ops R8 :$dst),
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"setl $dst", []>, TB; // R8 = < signed
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def SETLm : I<0x9C, MRM0m,
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(ops i8mem:$dst),
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"setl $dst", []>, TB; // [mem8] = < signed
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def SETGEr : I<0x9D, MRM0r,
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(ops R8 :$dst),
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"setge $dst", []>, TB; // R8 = >= signed
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def SETGEm : I<0x9D, MRM0m,
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(ops i8mem:$dst),
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"setge $dst", []>, TB; // [mem8] = >= signed
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def SETLEr : I<0x9E, MRM0r,
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(ops R8 :$dst),
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"setle $dst", []>, TB; // R8 = <= signed
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def SETLEm : I<0x9E, MRM0m,
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(ops i8mem:$dst),
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"setle $dst", []>, TB; // [mem8] = <= signed
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def SETGr : I<0x9F, MRM0r,
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(ops R8 :$dst),
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"setg $dst", []>, TB; // R8 = < signed
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def SETGm : I<0x9F, MRM0m,
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(ops i8mem:$dst),
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"setg $dst", []>, TB; // [mem8] = < signed
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// Integer comparisons
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def CMP8rr : I<0x38, MRMDestReg,
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