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Revert r162160 because it made a few buildbots fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162164 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8283,18 +8283,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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unsigned Opcode = 0;
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unsigned NumOperands = 0;
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// Truncate operations may prevent the merge of the SETCC instruction
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// and the arithmetic intruction before it. Attempt to truncate the operands
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// of the arithmetic instruction and use a reduced bit-width instruction.
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bool NeedTruncation = false;
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unsigned InOpcode = Op.getNode()->getOpcode();
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if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
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NeedTruncation = true;
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InOpcode = Op->getOperand(0)->getOpcode();
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}
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switch (InOpcode) {
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switch (Op.getNode()->getOpcode()) {
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case ISD::ADD:
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// Due to an isel shortcoming, be conservative if this add is likely to be
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// selected as part of a load-modify-store instruction. When the root node
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@ -8350,7 +8339,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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if (User->getOpcode() != ISD::BRCOND &&
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User->getOpcode() != ISD::SETCC &&
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!(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
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(User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
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NonFlagUse = true;
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break;
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}
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@ -8371,9 +8360,11 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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goto default_case;
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// Otherwise use a regular EFLAGS-setting instruction.
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switch (InOpcode) {
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switch (Op.getNode()->getOpcode()) {
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default: llvm_unreachable("unexpected operator!");
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case ISD::SUB: Opcode = X86ISD::SUB; break;
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case ISD::SUB:
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Opcode = X86ISD::SUB;
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break;
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case ISD::OR: Opcode = X86ISD::OR; break;
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case ISD::XOR: Opcode = X86ISD::XOR; break;
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case ISD::AND: Opcode = X86ISD::AND; break;
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@ -8394,34 +8385,6 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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break;
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}
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if (NeedTruncation) {
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SDValue WideVal = Op->getOperand(0);
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EVT VT = Op.getValueType();
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EVT WideVT = WideVal.getValueType();
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unsigned ConvertedOp = 0;
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// Use a target machine opcode to prevent further DAGCombine
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// optimizations that may separate the arithmetic operations from the
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// setcc node.
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switch (WideVal.getOpcode()) {
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default: break;
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case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
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case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
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case ISD::AND: ConvertedOp = X86ISD::AND; break;
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case ISD::OR: ConvertedOp = X86ISD::OR; break;
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case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
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}
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if (ConvertedOp && WideVal.hasOneUse()) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
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SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
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SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
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Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
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}
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}
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}
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if (Opcode == 0)
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// Emit a CMP with 0, which is the TEST pattern.
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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@ -1,45 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s
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; rdar://12081007
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; CHECK: and_1:
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; CHECK: andb
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; CHECK-NEXT: cmovnel
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; CHECK: ret
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define i32 @and_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
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%1 = and i8 %b, %a
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%2 = icmp ne i8 %1, 0
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%3 = select i1 %2, i32 %x, i32 0
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ret i32 %3
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}
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; CHECK: and_2:
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; CHECK: andb
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; CHECK-NEXT: setne
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; CHECK: ret
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define zeroext i1 @and_2(i8 zeroext %a, i8 zeroext %b) {
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%1 = and i8 %b, %a
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%2 = icmp ne i8 %1, 0
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ret i1 %2
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}
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; CHECK: xor_1:
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; CHECK: xorb
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; CHECK-NEXT: cmovnel
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; CHECK: ret
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define i32 @xor_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
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%1 = xor i8 %b, %a
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%2 = icmp ne i8 %1, 0
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%3 = select i1 %2, i32 %x, i32 0
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ret i32 %3
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}
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; CHECK: xor_2:
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; CHECK: xorb
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; CHECK-NEXT: setne
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; CHECK: ret
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define zeroext i1 @xor_2(i8 zeroext %a, i8 zeroext %b) {
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%1 = xor i8 %b, %a
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%2 = icmp ne i8 %1, 0
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ret i1 %2
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}
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@ -57,13 +57,13 @@ entry:
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%0 = load i32* %P, align 4
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%1 = load i32* %Q, align 4
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%2 = xor i32 %0, %1
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%3 = and i32 %2, 89947
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%3 = and i32 %2, 65535
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%4 = icmp eq i32 %3, 0
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br i1 %4, label %exit, label %land.end
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exit:
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%shr.i.i19 = xor i32 %1, %0
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%5 = and i32 %shr.i.i19, 3456789123
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%5 = and i32 %shr.i.i19, 2147418112
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%6 = icmp eq i32 %5, 0
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br label %land.end
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