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ARM assembly parsing and encoding for three-register VST1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-29 22:38:04 +00:00
parent 0edd83bfff
commit d5ca201891
4 changed files with 47 additions and 44 deletions
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8
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -269,8 +269,9 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,true},
{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, true, SingleSpc, 4, 1 ,true},
{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,true},
{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, true, SingleSpc, 3, 1 ,true},
{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, false, SingleSpc, 2, 4 ,false},
{ ARM::VST1q16PseudoWB_fixed, ARM::VST1q16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
@ -1186,7 +1187,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case ARM::VST3d8Pseudo_UPD:
case ARM::VST3d16Pseudo_UPD:
case ARM::VST3d32Pseudo_UPD:
case ARM::VST1d64TPseudo_UPD:
case ARM::VST1d64TPseudoWB_fixed:
case ARM::VST1d64TPseudoWB_register:
case ARM::VST3q8Pseudo_UPD:
case ARM::VST3q16Pseudo_UPD:
case ARM::VST3q32Pseudo_UPD:

3
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1579,6 +1579,7 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
}
return Opc; // If not one we handle, return it unchanged.
}
@ -2885,7 +2886,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case ARMISD::VST3_UPD: {
unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
ARM::VST3d32Pseudo_UPD,ARM::VST1d64TPseudoWB_fixed};
unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
ARM::VST3q16Pseudo_UPD,
ARM::VST3q32Pseudo_UPD };

52
lib/Target/ARM/ARMInstrNEON.td
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@ -1329,34 +1329,46 @@ def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
// ...with 3 registers
class VST1D3<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0110, op7_4, (outs),
(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
(ins addrmode6:$Rn, VecListThreeD:$Vd),
IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVSTInstruction";
}
class VST1D3WB<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm,
DPR:$Vd, DPR:$src2, DPR:$src3),
IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVSTInstruction";
multiclass VST1D3WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
"vst1", Dt, "$Vd, $Rn!",
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
IIC_VLD1x3u,
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
def VST1d8T : VST1D3<{0,0,0,?}, "8">;
def VST1d16T : VST1D3<{0,1,0,?}, "16">;
def VST1d32T : VST1D3<{1,0,0,?}, "32">;
def VST1d64T : VST1D3<{1,1,0,?}, "64">;
def VST1d8T : VST1D3<{0,0,0,?}, "8">;
def VST1d16T : VST1D3<{0,1,0,?}, "16">;
def VST1d32T : VST1D3<{1,0,0,?}, "32">;
def VST1d64T : VST1D3<{1,1,0,?}, "64">;
def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
// ...with 4 registers
class VST1D4<bits<4> op7_4, string Dt>

28
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2196,10 +2196,14 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::VST1q16wb_register:
case ARM::VST1q32wb_register:
case ARM::VST1q64wb_register:
case ARM::VST1d8T_UPD:
case ARM::VST1d16T_UPD:
case ARM::VST1d32T_UPD:
case ARM::VST1d64T_UPD:
case ARM::VST1d8Twb_fixed:
case ARM::VST1d16Twb_fixed:
case ARM::VST1d32Twb_fixed:
case ARM::VST1d64Twb_fixed:
case ARM::VST1d8Twb_register:
case ARM::VST1d16Twb_register:
case ARM::VST1d32Twb_register:
case ARM::VST1d64Twb_register:
case ARM::VST1d8Q_UPD:
case ARM::VST1d16Q_UPD:
case ARM::VST1d32Q_UPD:
@ -2264,14 +2268,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second input register
switch (Inst.getOpcode()) {
case ARM::VST1d8T:
case ARM::VST1d16T:
case ARM::VST1d32T:
case ARM::VST1d64T:
case ARM::VST1d8T_UPD:
case ARM::VST1d16T_UPD:
case ARM::VST1d32T_UPD:
case ARM::VST1d64T_UPD:
case ARM::VST1d8Q:
case ARM::VST1d16Q:
case ARM::VST1d32Q:
@ -2334,14 +2330,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Third input register
switch (Inst.getOpcode()) {
case ARM::VST1d8T:
case ARM::VST1d16T:
case ARM::VST1d32T:
case ARM::VST1d64T:
case ARM::VST1d8T_UPD:
case ARM::VST1d16T_UPD:
case ARM::VST1d32T_UPD:
case ARM::VST1d64T_UPD:
case ARM::VST1d8Q:
case ARM::VST1d16Q:
case ARM::VST1d32Q: