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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
ARM assembly parsing and encoding for three-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -269,8 +269,9 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,true},
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{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, true, SingleSpc, 4, 1 ,true},
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{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,true},
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{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, true, SingleSpc, 3, 1 ,true},
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{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
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{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
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{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
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{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, false, SingleSpc, 2, 4 ,false},
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{ ARM::VST1q16PseudoWB_fixed, ARM::VST1q16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
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@ -1186,7 +1187,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::VST3d8Pseudo_UPD:
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case ARM::VST3d16Pseudo_UPD:
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case ARM::VST3d32Pseudo_UPD:
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case ARM::VST1d64TPseudo_UPD:
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case ARM::VST1d64TPseudoWB_fixed:
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case ARM::VST1d64TPseudoWB_register:
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case ARM::VST3q8Pseudo_UPD:
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case ARM::VST3q16Pseudo_UPD:
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case ARM::VST3q32Pseudo_UPD:
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@ -1579,6 +1579,7 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
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case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
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case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
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case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
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case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
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}
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return Opc; // If not one we handle, return it unchanged.
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}
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@ -2885,7 +2886,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case ARMISD::VST3_UPD: {
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unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
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ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
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ARM::VST3d32Pseudo_UPD,ARM::VST1d64TPseudoWB_fixed};
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unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
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ARM::VST3q16Pseudo_UPD,
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ARM::VST3q32Pseudo_UPD };
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@ -1329,34 +1329,46 @@ def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
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// ...with 3 registers
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class VST1D3<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs),
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(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
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IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
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(ins addrmode6:$Rn, VecListThreeD:$Vd),
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IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVSTInstruction";
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}
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class VST1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm,
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DPR:$Vd, DPR:$src2, DPR:$src3),
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IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVSTInstruction";
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multiclass VST1D3WB<bits<4> op7_4, string Dt> {
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def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
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"vst1", Dt, "$Vd, $Rn!",
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"$Rn.addr = $wb", []> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
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IIC_VLD1x3u,
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"vst1", Dt, "$Vd, $Rn, $Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVSTInstruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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def VST1d8T : VST1D3<{0,0,0,?}, "8">;
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def VST1d16T : VST1D3<{0,1,0,?}, "16">;
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def VST1d32T : VST1D3<{1,0,0,?}, "32">;
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def VST1d64T : VST1D3<{1,1,0,?}, "64">;
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def VST1d8T : VST1D3<{0,0,0,?}, "8">;
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def VST1d16T : VST1D3<{0,1,0,?}, "16">;
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def VST1d32T : VST1D3<{1,0,0,?}, "32">;
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def VST1d64T : VST1D3<{1,1,0,?}, "64">;
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def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
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def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
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def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
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def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
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defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
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defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
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defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
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defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
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def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
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def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
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def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
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def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
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def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
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// ...with 4 registers
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class VST1D4<bits<4> op7_4, string Dt>
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@ -2196,10 +2196,14 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
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case ARM::VST1q16wb_register:
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case ARM::VST1q32wb_register:
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case ARM::VST1q64wb_register:
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case ARM::VST1d8T_UPD:
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case ARM::VST1d16T_UPD:
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case ARM::VST1d32T_UPD:
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case ARM::VST1d64T_UPD:
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case ARM::VST1d8Twb_fixed:
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case ARM::VST1d16Twb_fixed:
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case ARM::VST1d32Twb_fixed:
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case ARM::VST1d64Twb_fixed:
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case ARM::VST1d8Twb_register:
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case ARM::VST1d16Twb_register:
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case ARM::VST1d32Twb_register:
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case ARM::VST1d64Twb_register:
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case ARM::VST1d8Q_UPD:
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case ARM::VST1d16Q_UPD:
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case ARM::VST1d32Q_UPD:
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@ -2264,14 +2268,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
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// Second input register
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switch (Inst.getOpcode()) {
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case ARM::VST1d8T:
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case ARM::VST1d16T:
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case ARM::VST1d32T:
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case ARM::VST1d64T:
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case ARM::VST1d8T_UPD:
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case ARM::VST1d16T_UPD:
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case ARM::VST1d32T_UPD:
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case ARM::VST1d64T_UPD:
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case ARM::VST1d8Q:
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case ARM::VST1d16Q:
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case ARM::VST1d32Q:
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@ -2334,14 +2330,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
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// Third input register
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switch (Inst.getOpcode()) {
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case ARM::VST1d8T:
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case ARM::VST1d16T:
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case ARM::VST1d32T:
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case ARM::VST1d64T:
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case ARM::VST1d8T_UPD:
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case ARM::VST1d16T_UPD:
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case ARM::VST1d32T_UPD:
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case ARM::VST1d64T_UPD:
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case ARM::VST1d8Q:
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case ARM::VST1d16Q:
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case ARM::VST1d32Q:
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