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[PowerPC] MULHU/MULHS are not legal for vector types
I ran into some test failures where common code changed vector division by constant into a multiply-high operation (MULHU). But these are not implemented by the back-end, so we failed to recognize the insn. Fixed by marking MULHU/MULHS as Expand for vector types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214716 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -453,6 +453,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
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setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
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setOperationAction(ISD::MULHU, VT, Expand);
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setOperationAction(ISD::MULHS, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UDIVREM, VT, Expand);
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10
test/CodeGen/PowerPC/vec_urem_const.ll
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10
test/CodeGen/PowerPC/vec_urem_const.ll
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@ -0,0 +1,10 @@
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; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s
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; Common code used to replace the urem by a mulhu, and compilation would
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; then crash since mulhu isn't supported on vector types.
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define <4 x i32> @test(<4 x i32> %x) {
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entry:
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%0 = urem <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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ret <4 x i32> %0
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}
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