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Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with

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address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-03-20 21:57:36 +00:00
parent 4f4f93f9d6
commit d5fadaf56e
1 changed files with 47 additions and 0 deletions
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47
lib/Target/ARM/ARMInstrNEON.td
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@ -763,6 +763,21 @@ def VST2LNq32 : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; } def VST2LNq16odd : VST2LN<0b0101, "16"> { let Inst{5} = 1; }
def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; } def VST2LNq32odd : VST2LN<0b1001, "32"> { let Inst{6} = 1; }
// ...with address register writeback:
class VST2LNWB<bits<4> op11_8, string Dt>
: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
"\\{$src1[$lane], $src2[$lane]\\}, $addr",
"$addr.addr = $wb", []>;
def VST2LNd8_UPD : VST2LNWB<0b0001, "8">;
def VST2LNd16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 0; }
def VST2LNd32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 0; }
def VST2LNq16_UPD : VST2LNWB<0b0101, "16"> { let Inst{5} = 1; }
def VST2LNq32_UPD : VST2LNWB<0b1001, "32"> { let Inst{6} = 1; }
// VST3LN : Vector Store (single 3-element structure from one lane) // VST3LN : Vector Store (single 3-element structure from one lane)
class VST3LN<bits<4> op11_8, string Dt> class VST3LN<bits<4> op11_8, string Dt>
: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs), : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
@ -782,6 +797,22 @@ def VST3LNq32 : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; } def VST3LNq16odd : VST3LN<0b0110, "16"> { let Inst{5-4} = 0b10; }
def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; } def VST3LNq32odd : VST3LN<0b1010, "32"> { let Inst{6-4} = 0b100; }
// ...with address register writeback:
class VST3LNWB<bits<4> op11_8, string Dt>
: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
IIC_VST, "vst3", Dt,
"\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr",
"$addr.addr = $wb", []>;
def VST3LNd8_UPD : VST3LNWB<0b0010, "8"> { let Inst{4} = 0; }
def VST3LNd16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b00; }
def VST3LNd32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b000; }
def VST3LNq16_UPD : VST3LNWB<0b0110, "16"> { let Inst{5-4} = 0b10; }
def VST3LNq32_UPD : VST3LNWB<0b1010, "32"> { let Inst{6-4} = 0b100; }
// VST4LN : Vector Store (single 4-element structure from one lane) // VST4LN : Vector Store (single 4-element structure from one lane)
class VST4LN<bits<4> op11_8, string Dt> class VST4LN<bits<4> op11_8, string Dt>
: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs), : NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs),
@ -802,6 +833,22 @@ def VST4LNq32 : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; } def VST4LNq16odd : VST4LN<0b0111, "16"> { let Inst{5} = 1; }
def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; } def VST4LNq32odd : VST4LN<0b1011, "32"> { let Inst{6} = 1; }
// ...with address register writeback:
class VST4LNWB<bits<4> op11_8, string Dt>
: NLdSt<1, 0b00, op11_8, {?,?,?,?}, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
IIC_VST, "vst4", Dt,
"\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
"$addr.addr = $wb", []>;
def VST4LNd8_UPD : VST4LNWB<0b0011, "8">;
def VST4LNd16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 0; }
def VST4LNd32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 0; }
def VST4LNq16_UPD : VST4LNWB<0b0111, "16"> { let Inst{5} = 1; }
def VST4LNq32_UPD : VST4LNWB<0b1011, "32"> { let Inst{6} = 1; }
} // mayStore = 1, hasExtraSrcRegAllocReq = 1 } // mayStore = 1, hasExtraSrcRegAllocReq = 1