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https://github.com/c64scene-ar/llvm-6502.git
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llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -112,7 +112,7 @@ public:
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/// @note This has to exist, because this is a pass, but it should never be
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/// used.
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TargetData() : ImmutablePass(&ID) {
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llvm_report_error("ERROR: Bad TargetData ctor used. "
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llvm_report_error("Bad TargetData ctor used. "
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"Tool did not specify a TargetData to use?");
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}
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@ -5074,7 +5074,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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Input.ConstraintVT.isInteger()) ||
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(OpInfo.ConstraintVT.getSizeInBits() !=
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Input.ConstraintVT.getSizeInBits())) {
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llvm_report_error("llvm: error: Unsupported asm: input constraint"
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llvm_report_error("Unsupported asm: input constraint"
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" with a matching output constraint of incompatible"
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" type!");
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}
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@ -5179,7 +5179,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// Copy the output from the appropriate register. Find a register that
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// we can use.
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if (OpInfo.AssignedRegs.Regs.empty()) {
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llvm_report_error("llvm: error: Couldn't allocate output reg for"
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llvm_report_error("Couldn't allocate output reg for"
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" constraint '" + OpInfo.ConstraintCode + "'!");
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}
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@ -5233,8 +5233,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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|| (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
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// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
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if (OpInfo.isIndirect) {
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llvm_report_error("llvm: error: "
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"Don't know how to handle tied indirect "
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llvm_report_error("Don't know how to handle tied indirect "
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"register inputs yet!");
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}
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RegsForValue MatchedRegs;
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@ -5277,7 +5276,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
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hasMemory, Ops, DAG);
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if (Ops.empty()) {
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llvm_report_error("llvm: error: Invalid operand for inline asm"
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llvm_report_error("Invalid operand for inline asm"
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" constraint '" + OpInfo.ConstraintCode + "'!");
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}
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@ -5308,7 +5307,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// Copy the input into the appropriate registers.
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if (OpInfo.AssignedRegs.Regs.empty()) {
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llvm_report_error("llvm: error: Couldn't allocate input reg for"
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llvm_report_error("Couldn't allocate input reg for"
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" constraint '"+ OpInfo.ConstraintCode +"'!");
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}
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@ -644,7 +644,7 @@ void Interpreter::visitUnwindInst(UnwindInst &I) {
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}
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void Interpreter::visitUnreachableInst(UnreachableInst &I) {
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llvm_report_error("ERROR: Program executed an 'unreachable' instruction!");
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llvm_report_error("Program executed an 'unreachable' instruction!");
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}
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void Interpreter::visitBranchInst(BranchInst &I) {
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@ -141,7 +141,7 @@ void *JIT::getPointerToNamedFunction(const std::string &Name,
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return RP;
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if (AbortOnFailure) {
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llvm_report_error("ERROR: Program used external function '"+Name+
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llvm_report_error("Program used external function '"+Name+
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"' which could not be resolved!");
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}
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return 0;
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@ -749,7 +749,7 @@ void Emitter<CodeEmitter>::emitDataProcessingInstruction(
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const TargetInstrDesc &TID = MI.getDesc();
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if (TID.Opcode == ARM::BFC) {
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llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
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llvm_report_error("ARMv6t2 JIT is not yet supported.");
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}
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// Part of binary is determined by TableGn.
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