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Make CALL node consistent with RET node. Signness of value has type MVT::i32

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instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-05-26 23:13:20 +00:00
parent 6848be1a27
commit d61c4820c9
1 changed files with 5 additions and 5 deletions
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10
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@@ -2515,7 +2515,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
default: assert(0 && "Unknown type action!"); default: assert(0 && "Unknown type action!");
case Legal: case Legal:
Ops.push_back(Op); Ops.push_back(Op);
Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
break; break;
case Promote: case Promote:
if (MVT::isInteger(VT)) { if (MVT::isInteger(VT)) {
@@ -2526,7 +2526,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
} }
Ops.push_back(Op); Ops.push_back(Op);
Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
break; break;
case Expand: case Expand:
if (VT != MVT::Vector) { if (VT != MVT::Vector) {
@@ -2544,9 +2544,9 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
std::swap(Lo, Hi); std::swap(Lo, Hi);
Ops.push_back(Lo); Ops.push_back(Lo);
Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Ops.push_back(Hi); Ops.push_back(Hi);
Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
} else { } else {
// Value scalarized into many values. Unimp for now. // Value scalarized into many values. Unimp for now.
assert(0 && "Cannot expand i64 -> i16 yet!"); assert(0 && "Cannot expand i64 -> i16 yet!");
@@ -2565,7 +2565,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
// Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
Ops.push_back(Op); Ops.push_back(Op);
Ops.push_back(DAG.getConstant(isSigned, MVT::i1)); Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
} else { } else {
assert(0 && "Don't support illegal by-val vector call args yet!"); assert(0 && "Don't support illegal by-val vector call args yet!");
abort(); abort();