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Don't cache the TLI object since we have access to it through TargetMachine already.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184346 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-06-19 20:32:16 +00:00
parent c896020dd8
commit d626d33246
2 changed files with 9 additions and 8 deletions
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3
include/llvm/CodeGen/FunctionLoweringInfo.h
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@ -50,7 +50,6 @@ class Value;
///
class FunctionLoweringInfo {
const TargetMachine &TM;
const TargetLowering *TLI;
public:
const Function *Fn;
MachineFunction *MF;
@ -116,7 +115,7 @@ public:
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
explicit FunctionLoweringInfo(const TargetMachine &TM);
explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
/// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction.

14
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -55,15 +55,12 @@ static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
return false;
}
FunctionLoweringInfo::FunctionLoweringInfo(const TargetMachine &TM)
: TM(TM), TLI(0) {
}
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
const TargetLowering *TLI = TM.getTargetLowering();
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
TLI = TM.getTargetLowering();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
@ -209,7 +206,8 @@ void FunctionLoweringInfo::clear() {
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT));
return RegInfo->
createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
}
/// CreateRegs - Allocate the appropriate number of virtual registers of
@ -220,6 +218,8 @@ unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
const TargetLowering *TLI = TM.getTargetLowering();
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
@ -267,6 +267,8 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
if (!Ty->isIntegerTy() || Ty->isVectorTy())
return;
const TargetLowering *TLI = TM.getTargetLowering();
SmallVector<EVT, 1> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
assert(ValueVTs.size() == 1 &&