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https://github.com/c64scene-ar/llvm-6502.git
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PTX: Improve support for 64-bit addressing
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses - Add comparison selection for i64 - Add zext selection for i32 -> i64 - Add shl/shr/sha support for i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
fa4ebd396d
commit
d662576671
@ -130,8 +130,11 @@ bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
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return false;
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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@ -143,8 +146,12 @@ bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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if (isImm(Addr))
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return false;
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// it is [reg]
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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@ -177,7 +184,10 @@ bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
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// is [imm]?
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if (SelectImm(Addr, Base)) {
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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@ -194,7 +204,8 @@ bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
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return false;
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ConstantSDNode *CN = cast<ConstantSDNode>(node);
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imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(), MVT::i32);
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imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(),
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operand.getValueType());
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return true;
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}
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@ -41,6 +41,7 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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// Customize translation of memory addresses
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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// Expand BR_CC into BRCOND
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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@ -85,10 +86,12 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
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SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
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SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
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dl,
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MVT::i32,
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PtrVT.getSimpleVT(),
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targetGlobal);
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return movInstr;
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@ -285,18 +285,42 @@ multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
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}
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multiclass INT3ntnc<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def ri : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def ir : InstPTX<(outs RRegu32:$d),
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(ins i32imm:$a, RRegu32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
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def rr16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, RRegu16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
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def rr32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, RRegu32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
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def rr64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, RRegu64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
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def ri16 : InstPTX<(outs RRegu16:$d),
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(ins RRegu16:$a, i16imm:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
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def ri32 : InstPTX<(outs RRegu32:$d),
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(ins RRegu32:$a, i32imm:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
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def ri64 : InstPTX<(outs RRegu64:$d),
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(ins RRegu64:$a, i64imm:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
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def ir16 : InstPTX<(outs RRegu16:$d),
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(ins i16imm:$a, RRegu16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
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def ir32 : InstPTX<(outs RRegu32:$d),
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(ins i32imm:$a, RRegu32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
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def ir64 : InstPTX<(outs RRegu64:$d),
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(ins i64imm:$a, RRegu64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
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}
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multiclass PTX_SETP<RegisterClass RC, string regclsname, Operand immcls,
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@ -487,12 +511,18 @@ defm SETPLTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULT, "lt">;
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defm SETPLEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULE, "le">;
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defm SETPGTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGT, "gt">;
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defm SETPGEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGE, "ge">;
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defm SETPEQu64 : PTX_SETP<RRegu64, "u64", i64imm, SETEQ, "eq">;
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defm SETPNEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETNE, "ne">;
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defm SETPLTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULT, "lt">;
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defm SETPLEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULE, "le">;
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defm SETPGTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGT, "gt">;
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defm SETPGEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGE, "ge">;
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///===- Logic and Shift Instructions --------------------------------------===//
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defm SHL : INT3ntnc<"shl.b32", PTXshl>;
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defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
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defm SRA : INT3ntnc<"shr.s32", PTXsra>;
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defm SHL : INT3ntnc<"shl.b", PTXshl>;
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defm SRL : INT3ntnc<"shr.u", PTXsrl>;
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defm SRA : INT3ntnc<"shr.s", PTXsra>;
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defm AND : PTX_LOGIC<"and", and>;
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defm OR : PTX_LOGIC<"or", or>;
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@ -537,9 +567,12 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVaddr
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def MOVaddr32
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: InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
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[(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
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def MOVaddr64
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: InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
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[(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
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}
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// Loads
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@ -573,6 +606,10 @@ def CVT_u32_pred
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: InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
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[(set RRegu32:$d, (zext Preds:$a))]>;
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def CVT_u64_u32
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: InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
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[(set RRegu64:$d, (zext RRegu32:$a))]>;
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///===- Control Flow Instructions -----------------------------------------===//
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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