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PTX: Improve support for 64-bit addressing

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- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2011-03-23 16:58:51 +00:00
parent fa4ebd396d
commit d662576671
3 changed files with 72 additions and 21 deletions
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19
lib/Target/PTX/PTXISelDAGToDAG.cpp
View File

@ -130,8 +130,11 @@ bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
return false;
assert(Addr.getValueType().isSimple() && "Type must be simple");
R1 = Addr;
R2 = CurDAG->getTargetConstant(0, MVT::i32);
R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
return true;
}
@ -143,8 +146,12 @@ bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
if (isImm(Addr))
return false;
// it is [reg]
assert(Addr.getValueType().isSimple() && "Type must be simple");
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
return true;
}
@ -177,7 +184,10 @@ bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
// is [imm]?
if (SelectImm(Addr, Base)) {
Offset = CurDAG->getTargetConstant(0, MVT::i32);
assert(Addr.getValueType().isSimple() && "Type must be simple");
Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
return true;
}
@ -194,7 +204,8 @@ bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
return false;
ConstantSDNode *CN = cast<ConstantSDNode>(node);
imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(), MVT::i32);
imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(),
operand.getValueType());
return true;
}

5
lib/Target/PTX/PTXISelLowering.cpp
View File

@ -41,6 +41,7 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
// Customize translation of memory addresses
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
// Expand BR_CC into BRCOND
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
@ -85,10 +86,12 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
dl,
MVT::i32,
PtrVT.getSimpleVT(),
targetGlobal);
return movInstr;

69
lib/Target/PTX/PTXInstrInfo.td
View File

@ -285,18 +285,42 @@ multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
}
multiclass INT3ntnc<string opcstr, SDNode opnode> {
def rr : InstPTX<(outs RRegu32:$d),
(ins RRegu32:$a, RRegu32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
def ri : InstPTX<(outs RRegu32:$d),
(ins RRegu32:$a, i32imm:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
def ir : InstPTX<(outs RRegu32:$d),
(ins i32imm:$a, RRegu32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
def rr16 : InstPTX<(outs RRegu16:$d),
(ins RRegu16:$a, RRegu16:$b),
!strconcat(opcstr, "16\t$d, $a, $b"),
[(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
def rr32 : InstPTX<(outs RRegu32:$d),
(ins RRegu32:$a, RRegu32:$b),
!strconcat(opcstr, "32\t$d, $a, $b"),
[(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
def rr64 : InstPTX<(outs RRegu64:$d),
(ins RRegu64:$a, RRegu64:$b),
!strconcat(opcstr, "64\t$d, $a, $b"),
[(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
def ri16 : InstPTX<(outs RRegu16:$d),
(ins RRegu16:$a, i16imm:$b),
!strconcat(opcstr, "16\t$d, $a, $b"),
[(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
def ri32 : InstPTX<(outs RRegu32:$d),
(ins RRegu32:$a, i32imm:$b),
!strconcat(opcstr, "32\t$d, $a, $b"),
[(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
def ri64 : InstPTX<(outs RRegu64:$d),
(ins RRegu64:$a, i64imm:$b),
!strconcat(opcstr, "64\t$d, $a, $b"),
[(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
def ir16 : InstPTX<(outs RRegu16:$d),
(ins i16imm:$a, RRegu16:$b),
!strconcat(opcstr, "16\t$d, $a, $b"),
[(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
def ir32 : InstPTX<(outs RRegu32:$d),
(ins i32imm:$a, RRegu32:$b),
!strconcat(opcstr, "32\t$d, $a, $b"),
[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
def ir64 : InstPTX<(outs RRegu64:$d),
(ins i64imm:$a, RRegu64:$b),
!strconcat(opcstr, "64\t$d, $a, $b"),
[(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
}
multiclass PTX_SETP<RegisterClass RC, string regclsname, Operand immcls,
@ -487,12 +511,18 @@ defm SETPLTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULT, "lt">;
defm SETPLEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULE, "le">;
defm SETPGTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGT, "gt">;
defm SETPGEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGE, "ge">;
defm SETPEQu64 : PTX_SETP<RRegu64, "u64", i64imm, SETEQ, "eq">;
defm SETPNEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETNE, "ne">;
defm SETPLTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULT, "lt">;
defm SETPLEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETULE, "le">;
defm SETPGTu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGT, "gt">;
defm SETPGEu64 : PTX_SETP<RRegu64, "u64", i64imm, SETUGE, "ge">;
///===- Logic and Shift Instructions --------------------------------------===//
defm SHL : INT3ntnc<"shl.b32", PTXshl>;
defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
defm SRA : INT3ntnc<"shr.s32", PTXsra>;
defm SHL : INT3ntnc<"shl.b", PTXshl>;
defm SRL : INT3ntnc<"shr.u", PTXsrl>;
defm SRA : INT3ntnc<"shr.s", PTXsra>;
defm AND : PTX_LOGIC<"and", and>;
defm OR : PTX_LOGIC<"or", or>;
@ -537,9 +567,12 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def MOVaddr
def MOVaddr32
: InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
[(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
def MOVaddr64
: InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
[(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
}
// Loads
@ -573,6 +606,10 @@ def CVT_u32_pred
: InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
[(set RRegu32:$d, (zext Preds:$a))]>;
def CVT_u64_u32
: InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
[(set RRegu64:$d, (zext RRegu32:$a))]>;
///===- Control Flow Instructions -----------------------------------------===//
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {