mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
Added encoding bits for the Thumb ISA. Initial checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
parent
a0cefcfcac
commit
d68e119c0f
@ -146,11 +146,9 @@ def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
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// ARM Instruction templates.
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//
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class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "ARM";
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// TSFlagsFields
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@ -179,6 +177,20 @@ class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
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let Itinerary = itin;
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}
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class Encoding {
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field bits<32> Inst;
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}
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class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
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// This Encoding-less class is used by Thumb1 to specify the encoding bits later
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// on by adding flavors to specific instructions.
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class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: InstTemplate<am, sz, im, f, d, cstr, itin>;
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class PseudoInst<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
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@ -861,7 +873,7 @@ class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
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class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin, string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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@ -876,9 +888,14 @@ class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
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// tBL, tBX instructions
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class TIx2<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
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// tBL, tBX 32-bit instructions
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class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
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dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
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let Inst{31-27} = opcod1;
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let Inst{15-14} = opcod2;
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let Inst{12} = opcod3;
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}
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// BR_JT instructions
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class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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@ -887,7 +904,7 @@ class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> patter
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// Thumb1 only
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class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin, string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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let AsmString = asm;
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@ -903,7 +920,8 @@ class T1Ix2<dag oops, dag iops, InstrItinClass itin,
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: Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
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class T1JTI<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
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: Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>,
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Encoding;
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// Two-address instructions
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class T1It<dag oops, dag iops, InstrItinClass itin,
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@ -915,7 +933,7 @@ class T1It<dag oops, dag iops, InstrItinClass itin,
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class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = !con(oops, (ops s_cc_out:$s));
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let InOperandList = !con(iops, (ops pred:$p));
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let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
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@ -937,7 +955,7 @@ class T1sIt<dag oops, dag iops, InstrItinClass itin,
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class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ops pred:$p));
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let AsmString = !strconcat(opc, !strconcat("${p}", asm));
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@ -968,6 +986,46 @@ class T1pIs<dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
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// A6.2 16-bit Thumb instruction encoding
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class T1Encoding<bits<6> opcode> : Encoding {
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let Inst{15-10} = opcode;
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}
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// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
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class T1General<bits<5> opcode> : Encoding {
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let Inst{15-14} = 0b00;
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let Inst{13-9} = opcode;
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}
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// A6.2.2 Data-processing encoding.
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class T1DataProcessing<bits<4> opcode> : Encoding {
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let Inst{15-10} = 0b010000;
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let Inst{9-6} = opcode;
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}
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// A6.2.3 Special data instructions and branch and exchange encoding.
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class T1Special<bits<4> opcode> : Encoding {
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let Inst{15-10} = 0b010001;
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let Inst{9-6} = opcode;
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}
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// A6.2.4 Load/store single data item encoding.
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class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding {
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let Inst{15-12} = opA;
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let Inst{11-9} = opB;
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}
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class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
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class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
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class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
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class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
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class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
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// A6.2.5 Miscellaneous 16-bit instructions encoding.
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class T1Misc<bits<7> opcode> : Encoding {
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let Inst{15-12} = 0b1011;
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let Inst{11-5} = opcode;
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}
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// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
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class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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@ -1034,9 +1092,18 @@ class T2Iso<dag oops, dag iops, InstrItinClass itin,
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class T2Ipc<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
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class T2Ii8s4<dag oops, dag iops, InstrItinClass itin,
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class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", pattern>;
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: Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
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pattern> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24} = P;
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let Inst{23} = ?; // The U bit.
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let Inst{22} = 1;
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let Inst{21} = W;
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let Inst{20} = load;
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}
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class T2sI<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -1055,8 +1122,9 @@ class T2Ix2<dag oops, dag iops, InstrItinClass itin,
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// T2Iidxldst - Thumb2 indexed load / store instructions.
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class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im,
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InstrItinClass itin,
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class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
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dag oops, dag iops,
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AddrMode am, IndexMode im, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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@ -1064,6 +1132,16 @@ class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im,
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let AsmString = !strconcat(opc, !strconcat("${p}", asm));
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb2];
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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let Inst{23} = 0;
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let Inst{22-21} = opcod;
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let Inst{20} = load;
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let Inst{11} = 1;
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// (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
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let Inst{10} = pre; // The P bit.
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let Inst{8} = 1; // The W bit.
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}
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// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
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@ -136,31 +136,46 @@ PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
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let isNotDuplicable = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
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"\n$cp:\n\tadd\t$dst, pc",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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T1Special<{0,0,?,?}> {
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let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
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}
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// PC relative add.
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, pc, $rhs", []>;
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"add\t$dst, pc, $rhs", []>,
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T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
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// ADD rd, sp, #imm8
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, $sp, $rhs", []>;
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"add\t$dst, $sp, $rhs", []>,
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T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
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// ADD sp, sp, #imm7
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, $rhs", []>;
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"add\t$dst, $rhs", []>,
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T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
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// SUB sp, sp, #imm7
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def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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"sub\t$dst, $rhs", []>;
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"sub\t$dst, $rhs", []>,
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T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
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// ADD rm, sp
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def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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"add\t$dst, $rhs", []>;
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"add\t$dst, $rhs", []>,
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T1Special<{0,0,?,?}> {
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let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
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}
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// ADD sp, rm
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def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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"add\t$dst, $rhs", []>;
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"add\t$dst, $rhs", []>,
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T1Special<{0,0,?,?}> {
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// A8.6.9 Encoding T2
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let Inst{7} = 1;
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let Inst{2-0} = 0b101;
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}
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// Pseudo instruction that will expand into a tSUBspi + a copy.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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@ -180,22 +195,32 @@ def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>;
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def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
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T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
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let Inst{6-3} = 0b1110; // Rm = lr
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}
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>,
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T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
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[(brind GPR:$dst)]>;
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[(brind GPR:$dst)]>,
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T1Special<{1,0,?,?}> {
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// <Rd> = pc
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let Inst{7} = 1;
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let Inst{2-0} = 0b111;
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}
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
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"pop${p}\t$wb", []>;
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"pop${p}\t$wb", []>,
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T1Misc<{1,1,0,?,?,?,?}>;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R12, LR,
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@ -203,25 +228,29 @@ let isCall = 1,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
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// Also used for Thumb2
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def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"bl\t${func:call}",
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[(ARMtcall tglobaladdr:$func)]>,
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def tBL : TIx2<0b11110, 0b11, 1,
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(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"bl\t${func:call}",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb, IsNotDarwin]>;
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// ARMv5T and above, also used for Thumb2
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def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"blx\t${func:call}",
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[(ARMcall tglobaladdr:$func)]>,
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def tBLXi : TIx2<0b11110, 0b11, 0,
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(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"blx\t${func:call}",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]>;
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// Also used for Thumb2
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def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
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"blx\t$func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]>;
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Requires<[IsThumb, HasV5T, IsNotDarwin]>,
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T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
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// ARMv4T
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def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb1Only, IsNotDarwin]>;
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@ -234,27 +263,31 @@ let isCall = 1,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
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// Also used for Thumb2
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def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
|
||||
def tBLr9 : TIx2<0b11110, 0b11, 1,
|
||||
(outs), (ins i32imm:$func, variable_ops), IIC_Br,
|
||||
"bl\t${func:call}",
|
||||
[(ARMtcall tglobaladdr:$func)]>,
|
||||
Requires<[IsThumb, IsDarwin]>;
|
||||
|
||||
// ARMv5T and above, also used for Thumb2
|
||||
def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
|
||||
def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
|
||||
(outs), (ins i32imm:$func, variable_ops), IIC_Br,
|
||||
"blx\t${func:call}",
|
||||
[(ARMcall tglobaladdr:$func)]>,
|
||||
Requires<[IsThumb, HasV5T, IsDarwin]>;
|
||||
|
||||
// Also used for Thumb2
|
||||
def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
|
||||
"blx\t$func",
|
||||
[(ARMtcall GPR:$func)]>,
|
||||
Requires<[IsThumb, HasV5T, IsDarwin]>;
|
||||
"blx\t$func",
|
||||
[(ARMtcall GPR:$func)]>,
|
||||
Requires<[IsThumb, HasV5T, IsDarwin]>,
|
||||
T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
|
||||
|
||||
// ARMv4T
|
||||
def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
|
||||
"mov\tlr, pc\n\tbx\t$func",
|
||||
[(ARMcall_nolink tGPR:$func)]>,
|
||||
def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
|
||||
(outs), (ins tGPR:$func, variable_ops), IIC_Br,
|
||||
"mov\tlr, pc\n\tbx\t$func",
|
||||
[(ARMcall_nolink tGPR:$func)]>,
|
||||
Requires<[IsThumb1Only, IsDarwin]>;
|
||||
}
|
||||
|
||||
@ -262,11 +295,12 @@ let isBranch = 1, isTerminator = 1 in {
|
||||
let isBarrier = 1 in {
|
||||
let isPredicable = 1 in
|
||||
def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
|
||||
"b\t$target", [(br bb:$target)]>;
|
||||
"b\t$target", [(br bb:$target)]>,
|
||||
T1Encoding<{1,1,1,0,0,?}>;
|
||||
|
||||
// Far jump
|
||||
let Defs = [LR] in
|
||||
def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
|
||||
def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
|
||||
"bl\t$target\t@ far jump",[]>;
|
||||
|
||||
def tBR_JTr : T1JTI<(outs),
|
||||
@ -281,15 +315,18 @@ let isBranch = 1, isTerminator = 1 in {
|
||||
let isBranch = 1, isTerminator = 1 in
|
||||
def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
|
||||
"b$cc\t$target",
|
||||
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
|
||||
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
|
||||
T1Encoding<{1,1,0,1,?,?}>;
|
||||
|
||||
// Compare and branch on zero / non-zero
|
||||
let isBranch = 1, isTerminator = 1 in {
|
||||
def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
|
||||
"cbz\t$cmp, $target", []>;
|
||||
"cbz\t$cmp, $target", []>,
|
||||
T1Misc<{0,0,?,1,?,?,?}>;
|
||||
|
||||
def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
|
||||
"cbnz\t$cmp, $target", []>;
|
||||
"cbnz\t$cmp, $target", []>,
|
||||
T1Misc<{1,0,?,1,?,?,?}>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -299,71 +336,85 @@ let isBranch = 1, isTerminator = 1 in {
|
||||
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
||||
def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
|
||||
"ldr", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
|
||||
[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
|
||||
T1LdSt<0b100>;
|
||||
|
||||
def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
|
||||
"ldrb", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
|
||||
[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
|
||||
T1LdSt<0b110>;
|
||||
|
||||
def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
|
||||
"ldrh", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
|
||||
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
|
||||
T1LdSt<0b101>;
|
||||
|
||||
let AddedComplexity = 10 in
|
||||
def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
|
||||
"ldrsb", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
|
||||
[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
|
||||
T1LdSt<0b011>;
|
||||
|
||||
let AddedComplexity = 10 in
|
||||
def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
|
||||
"ldrsh", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
|
||||
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
|
||||
T1LdSt<0b111>;
|
||||
|
||||
let canFoldAsLoad = 1 in
|
||||
def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
|
||||
"ldr", "\t$dst, $addr",
|
||||
[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
|
||||
[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
|
||||
T1LdStSP<{1,?,?}>;
|
||||
|
||||
// Special instruction for restore. It cannot clobber condition register
|
||||
// when it's expanded by eliminateCallFramePseudoInstr().
|
||||
let canFoldAsLoad = 1, mayLoad = 1 in
|
||||
def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
|
||||
"ldr", "\t$dst, $addr", []>;
|
||||
"ldr", "\t$dst, $addr", []>,
|
||||
T1LdStSP<{1,?,?}>;
|
||||
|
||||
// Load tconstpool
|
||||
// FIXME: Use ldr.n to work around a Darwin assembler bug.
|
||||
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
||||
def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
|
||||
"ldr", ".n\t$dst, $addr",
|
||||
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
|
||||
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
|
||||
T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
|
||||
|
||||
// Special LDR for loads from non-pc-relative constpools.
|
||||
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
|
||||
mayHaveSideEffects = 1 in
|
||||
def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
|
||||
"ldr", "\t$dst, $addr", []>;
|
||||
"ldr", "\t$dst, $addr", []>,
|
||||
T1LdStSP<{1,?,?}>;
|
||||
|
||||
def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
|
||||
"str", "\t$src, $addr",
|
||||
[(store tGPR:$src, t_addrmode_s4:$addr)]>;
|
||||
[(store tGPR:$src, t_addrmode_s4:$addr)]>,
|
||||
T1LdSt<0b000>;
|
||||
|
||||
def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
|
||||
"strb", "\t$src, $addr",
|
||||
[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
|
||||
[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
|
||||
T1LdSt<0b010>;
|
||||
|
||||
def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
|
||||
"strh", "\t$src, $addr",
|
||||
[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
|
||||
[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
|
||||
T1LdSt<0b001>;
|
||||
|
||||
def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
|
||||
"str", "\t$src, $addr",
|
||||
[(store tGPR:$src, t_addrmode_sp:$addr)]>;
|
||||
[(store tGPR:$src, t_addrmode_sp:$addr)]>,
|
||||
T1LdStSP<{0,?,?}>;
|
||||
|
||||
let mayStore = 1 in {
|
||||
// Special instruction for spill. It cannot clobber condition register
|
||||
// when it's expanded by eliminateCallFramePseudoInstr().
|
||||
def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
|
||||
"str", "\t$src, $addr", []>;
|
||||
"str", "\t$src, $addr", []>,
|
||||
T1LdStSP<{0,?,?}>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -375,21 +426,25 @@ let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
||||
def tLDM : T1I<(outs),
|
||||
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
|
||||
IIC_iLoadm,
|
||||
"ldm${addr:submode}${p}\t$addr, $wb", []>;
|
||||
"ldm${addr:submode}${p}\t$addr, $wb", []>,
|
||||
T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
def tSTM : T1I<(outs),
|
||||
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
|
||||
IIC_iStorem,
|
||||
"stm${addr:submode}${p}\t$addr, $wb", []>;
|
||||
"stm${addr:submode}${p}\t$addr, $wb", []>,
|
||||
T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
|
||||
|
||||
let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
|
||||
def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
|
||||
"pop${p}\t$wb", []>;
|
||||
"pop${p}\t$wb", []>,
|
||||
T1Misc<{1,1,0,?,?,?,?}>;
|
||||
|
||||
let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
|
||||
def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
|
||||
"push${p}\t$wb", []>;
|
||||
"push${p}\t$wb", []>,
|
||||
T1Misc<{0,1,0,?,?,?,?}>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Arithmetic Instructions.
|
||||
@ -399,82 +454,98 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
|
||||
let isCommutable = 1, Uses = [CPSR] in
|
||||
def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"adc", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0101>;
|
||||
|
||||
// Add immediate
|
||||
def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
|
||||
"add", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
|
||||
T1General<0b01110>;
|
||||
|
||||
def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
|
||||
"add", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
|
||||
T1General<{1,1,0,?,?}>;
|
||||
|
||||
// Add register
|
||||
let isCommutable = 1 in
|
||||
def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"add", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1General<0b01100>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
|
||||
"add", "\t$dst, $rhs", []>;
|
||||
"add", "\t$dst, $rhs", []>,
|
||||
T1Special<{0,0,?,?}>;
|
||||
|
||||
// And register
|
||||
let isCommutable = 1 in
|
||||
def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"and", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0000>;
|
||||
|
||||
// ASR immediate
|
||||
def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
|
||||
"asr", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
|
||||
[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
|
||||
T1General<{0,1,0,?,?}>;
|
||||
|
||||
// ASR register
|
||||
def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
|
||||
"asr", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0100>;
|
||||
|
||||
// BIC register
|
||||
def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"bic", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
|
||||
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
|
||||
T1DataProcessing<0b1110>;
|
||||
|
||||
// CMN register
|
||||
let Defs = [CPSR] in {
|
||||
def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
|
||||
"cmn", "\t$lhs, $rhs",
|
||||
[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
|
||||
[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b1011>;
|
||||
def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
|
||||
"cmn", "\t$lhs, $rhs",
|
||||
[(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
|
||||
[(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b1011>;
|
||||
}
|
||||
|
||||
// CMP immediate
|
||||
let Defs = [CPSR] in {
|
||||
def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
|
||||
"cmp", "\t$lhs, $rhs",
|
||||
[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
|
||||
[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
|
||||
T1General<{1,0,1,?,?}>;
|
||||
def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
|
||||
"cmp", "\t$lhs, $rhs",
|
||||
[(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
|
||||
|
||||
[(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
|
||||
T1General<{1,0,1,?,?}>;
|
||||
}
|
||||
|
||||
// CMP register
|
||||
let Defs = [CPSR] in {
|
||||
def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
|
||||
"cmp", "\t$lhs, $rhs",
|
||||
[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
|
||||
[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
|
||||
T1DataProcessing<0b1010>;
|
||||
def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
|
||||
"cmp", "\t$lhs, $rhs",
|
||||
[(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
|
||||
[(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
|
||||
T1DataProcessing<0b1010>;
|
||||
|
||||
def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
|
||||
"cmp", "\t$lhs, $rhs", []>;
|
||||
"cmp", "\t$lhs, $rhs", []>,
|
||||
T1Special<{0,1,?,?}>;
|
||||
def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
|
||||
"cmp", "\t$lhs, $rhs", []>;
|
||||
"cmp", "\t$lhs, $rhs", []>,
|
||||
T1Special<{0,1,?,?}>;
|
||||
}
|
||||
|
||||
|
||||
@ -482,32 +553,38 @@ def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
|
||||
let isCommutable = 1 in
|
||||
def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"eor", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0001>;
|
||||
|
||||
// LSL immediate
|
||||
def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
|
||||
"lsl", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
||||
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
|
||||
T1General<{0,0,0,?,?}>;
|
||||
|
||||
// LSL register
|
||||
def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
|
||||
"lsl", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0010>;
|
||||
|
||||
// LSR immediate
|
||||
def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
|
||||
"lsr", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
||||
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
|
||||
T1General<{0,0,1,?,?}>;
|
||||
|
||||
// LSR register
|
||||
def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
|
||||
"lsr", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0011>;
|
||||
|
||||
// move register
|
||||
def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
|
||||
"mov", "\t$dst, $src",
|
||||
[(set tGPR:$dst, imm0_255:$src)]>;
|
||||
[(set tGPR:$dst, imm0_255:$src)]>,
|
||||
T1General<{1,0,0,?,?}>;
|
||||
|
||||
// TODO: A7-73: MOV(2) - mov setting flag.
|
||||
|
||||
@ -515,42 +592,52 @@ def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
|
||||
let neverHasSideEffects = 1 in {
|
||||
// FIXME: Make this predicable.
|
||||
def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
|
||||
"mov\t$dst, $src", []>;
|
||||
"mov\t$dst, $src", []>,
|
||||
T1Special<0b1000>;
|
||||
let Defs = [CPSR] in
|
||||
def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
|
||||
"movs\t$dst, $src", []>;
|
||||
"movs\t$dst, $src", []>, Encoding {
|
||||
let Inst{15-6} = 0b0000000000;
|
||||
}
|
||||
|
||||
// FIXME: Make these predicable.
|
||||
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
|
||||
"mov\t$dst, $src", []>;
|
||||
"mov\t$dst, $src", []>,
|
||||
T1Special<{1,0,0,1}>;
|
||||
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
|
||||
"mov\t$dst, $src", []>;
|
||||
"mov\t$dst, $src", []>,
|
||||
T1Special<{1,0,1,0}>;
|
||||
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
|
||||
"mov\t$dst, $src", []>;
|
||||
"mov\t$dst, $src", []>,
|
||||
T1Special<{1,0,1,1}>;
|
||||
} // neverHasSideEffects
|
||||
|
||||
// multiply register
|
||||
let isCommutable = 1 in
|
||||
def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
|
||||
"mul", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b1101>;
|
||||
|
||||
// move inverse register
|
||||
def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
|
||||
"mvn", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (not tGPR:$src))]>;
|
||||
[(set tGPR:$dst, (not tGPR:$src))]>,
|
||||
T1DataProcessing<0b1111>;
|
||||
|
||||
// bitwise or register
|
||||
let isCommutable = 1 in
|
||||
def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"orr", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b1100>;
|
||||
|
||||
// swaps
|
||||
def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"rev", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (bswap tGPR:$src))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{1,0,1,0,0,0,?}>;
|
||||
|
||||
def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"rev16", "\t$dst, $src",
|
||||
@ -559,7 +646,8 @@ def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
|
||||
(or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
|
||||
(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{1,0,1,0,0,1,?}>;
|
||||
|
||||
def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"revsh", "\t$dst, $src",
|
||||
@ -567,37 +655,44 @@ def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
(sext_inreg
|
||||
(or (srl (and tGPR:$src, 0xFF00), (i32 8)),
|
||||
(shl tGPR:$src, (i32 8))), i16))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{1,0,1,0,1,1,?}>;
|
||||
|
||||
// rotate right register
|
||||
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
|
||||
"ror", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0111>;
|
||||
|
||||
// negate register
|
||||
def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
|
||||
"rsb", "\t$dst, $src, #0",
|
||||
[(set tGPR:$dst, (ineg tGPR:$src))]>;
|
||||
[(set tGPR:$dst, (ineg tGPR:$src))]>,
|
||||
T1DataProcessing<0b1001>;
|
||||
|
||||
// Subtract with carry register
|
||||
let Uses = [CPSR] in
|
||||
def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"sbc", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1DataProcessing<0b0110>;
|
||||
|
||||
// Subtract immediate
|
||||
def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
|
||||
"sub", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
|
||||
T1General<0b01111>;
|
||||
|
||||
def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
|
||||
"sub", "\t$dst, $rhs",
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
|
||||
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
|
||||
T1General<{1,1,1,?,?}>;
|
||||
|
||||
// subtract register
|
||||
def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
"sub", "\t$dst, $lhs, $rhs",
|
||||
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
|
||||
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
|
||||
T1General<0b01101>;
|
||||
|
||||
// TODO: A7-96: STMIA - store multiple.
|
||||
|
||||
@ -605,31 +700,36 @@ def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
|
||||
def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"sxtb", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{0,0,1,0,0,1,?}>;
|
||||
|
||||
// sign-extend short
|
||||
def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"sxth", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{0,0,1,0,0,0,?}>;
|
||||
|
||||
// test
|
||||
let isCommutable = 1, Defs = [CPSR] in
|
||||
def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
|
||||
"tst", "\t$lhs, $rhs",
|
||||
[(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
|
||||
[(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
|
||||
T1DataProcessing<0b1000>;
|
||||
|
||||
// zero-extend byte
|
||||
def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"uxtb", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{0,0,1,0,1,1,?}>;
|
||||
|
||||
// zero-extend short
|
||||
def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
|
||||
"uxth", "\t$dst, $src",
|
||||
[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
|
||||
Requires<[IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb1Only, HasV6]>,
|
||||
T1Misc<{0,0,1,0,1,0,?}>;
|
||||
|
||||
|
||||
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
|
||||
@ -643,19 +743,23 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
|
||||
|
||||
// 16-bit movcc in IT blocks for Thumb2.
|
||||
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
|
||||
"mov", "\t$dst, $rhs", []>;
|
||||
"mov", "\t$dst, $rhs", []>,
|
||||
T1Special<{1,0,?,?}>;
|
||||
|
||||
def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
|
||||
"mov", "\t$dst, $rhs", []>;
|
||||
"mov", "\t$dst, $rhs", []>,
|
||||
T1General<{1,0,0,?,?}>;
|
||||
|
||||
// tLEApcrel - Load a pc-relative address into a register without offending the
|
||||
// assembler.
|
||||
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
|
||||
"adr$p\t$dst, #$label", []>;
|
||||
"adr$p\t$dst, #$label", []>,
|
||||
T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
|
||||
|
||||
def tLEApcrelJT : T1I<(outs tGPR:$dst),
|
||||
(ins i32imm:$label, nohash_imm:$id, pred:$p),
|
||||
IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>;
|
||||
IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
|
||||
T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// TLS Instructions
|
||||
@ -664,9 +768,9 @@ def tLEApcrelJT : T1I<(outs tGPR:$dst),
|
||||
// __aeabi_read_tp preserves the registers r1-r3.
|
||||
let isCall = 1,
|
||||
Defs = [R0, LR] in {
|
||||
def tTPsoft : TIx2<(outs), (ins), IIC_Br,
|
||||
"bl\t__aeabi_read_tp",
|
||||
[(set R0, ARMthread_pointer)]>;
|
||||
def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
|
||||
"bl\t__aeabi_read_tp",
|
||||
[(set R0, ARMthread_pointer)]>;
|
||||
}
|
||||
|
||||
// SJLJ Exception handling intrinsics
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user