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PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79415 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2009-08-19 08:46:10 +00:00
parent 6793dd9769
commit d68eea2b6d
2 changed files with 17 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3466,7 +3466,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Is the shift amount a multiple of size of VT?
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
if (N0.getValueType().getSizeInBits() <= EVTBits)
// Is the load width a multiple of size of VT?
if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
return SDValue();
}
}

15
test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s
@a = external global i96, align 4
@b = external global i64, align 8
define void @c() nounwind {
; CHECK: movl a+8, %eax
%srcval1 = load i96* @a, align 4
%sroa.store.elt2 = lshr i96 %srcval1, 64
%tmp = trunc i96 %sroa.store.elt2 to i64
; CHECK: movl %eax, b
; CHECK: movl $0, b+4
store i64 %tmp, i64* @b, align 8
ret void
}