From d6a80778e5a5fab339036b2f462d3039efe28a08 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 30 Aug 2005 22:38:05 +0000
Subject: [PATCH] Allow physregs to occur in the dag with multiple types. 
 Though I don't like this, it is a requirement on PPC, which can have an f32
 value in r3 at one point in a function and a f64 value in r3 at another
 point.  :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23160 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/SelectionDAG.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 8008a4b59a1..ed27fb11054 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -355,7 +355,7 @@ private:
   std::map<std::pair<unsigned, std::pair<SDOperand, SDOperand> >,
            SDNode *> BinaryOps;
 
-  std::vector<RegisterSDNode*> RegNodes;
+  std::map<std::pair<unsigned, MVT::ValueType>, RegisterSDNode*> RegNodes;
   std::vector<CondCodeSDNode*> CondCodeNodes;
 
   std::map<std::pair<SDOperand, std::pair<SDOperand, MVT::ValueType> >,