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Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,20 +20,6 @@ include "llvm/Target/Target.td"
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// ARM Subtarget features.
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//
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def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
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"ARM v4T">;
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def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
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"ARM v5T">;
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def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2">;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A">;
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def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
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"ARM v7M">;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
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@ -46,10 +32,10 @@ def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision floating point">;
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def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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"Enable Thumb2 extract and pack instructions">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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@ -59,18 +45,40 @@ def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
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// others as well. We should do more benchmarking and confirm one way or
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// the other.
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def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
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"Disable VFP MAC instructions">;
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def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
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"Disable VFP MAC instructions">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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// ARM architectures.
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def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
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"ARM v4T">;
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def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
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"ARM v5T">;
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def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
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"ARM v6m",
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[FeatureDB]>;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2">;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A",
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[FeatureDB]>;
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def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
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"ARM v7M",
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[FeatureDB]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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@ -128,7 +136,7 @@ def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
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// V6M Processors.
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def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6, FeatureDB]>;
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def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries,
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@ -139,17 +147,13 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries,
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
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FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack,
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FeatureDB]>;
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FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack,
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FeatureDB]>;
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2XtPk]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv,
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FeatureDB]>;
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def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv,
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FeatureDB]>;
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def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
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def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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@ -26,7 +26,7 @@ class GlobalValue;
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class ARMSubtarget : public TargetSubtarget {
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protected:
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enum ARMArchEnum {
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V4, V4T, V5T, V5TE, V6, V6T2, V7A, V7M
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V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
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};
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enum ARMFPEnum {
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0
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; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M
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declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
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@ -7,8 +7,8 @@ define void @t1() {
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; V6: t1:
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; V6: blx {{_*}}sync_synchronize
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; M0: t1:
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; M0: dsb
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; V6M: t1:
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; V6M: dsb
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call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
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ret void
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}
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@ -17,8 +17,8 @@ define void @t2() {
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; V6: t2:
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; V6: blx {{_*}}sync_synchronize
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; M0: t2:
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; M0: dmb
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; V6M: t2:
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; V6M: dmb
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call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
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ret void
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}
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