From d6e488d19701dc1aa90265be139770656ec40066 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 1 Nov 2013 17:13:42 +0000 Subject: [PATCH] [AArch64] Fix assembly string formatting and other coding standard violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193866 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64InstrNEON.td | 308 ++++++++++--------------- 1 file changed, 118 insertions(+), 190 deletions(-) diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 183fbb6b4d9..d96df10d193 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -58,8 +58,7 @@ def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2, multiclass NeonI_3VSame_B_sizes size, bits<5> opcode, string asmop, SDPatternOperator opnode8B, SDPatternOperator opnode16B, - bit Commutable = 0> -{ + bit Commutable = 0> { let isCommutable = Commutable in { def _8B : NeonI_3VSame<0b0, u, size, opcode, (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm), @@ -80,8 +79,7 @@ multiclass NeonI_3VSame_B_sizes size, bits<5> opcode, multiclass NeonI_3VSame_HS_sizes opcode, string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ + bit Commutable = 0> { let isCommutable = Commutable in { def _4H : NeonI_3VSame<0b0, u, 0b01, opcode, (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm), @@ -115,8 +113,7 @@ multiclass NeonI_3VSame_HS_sizes opcode, multiclass NeonI_3VSame_BHS_sizes opcode, string asmop, SDPatternOperator opnode, bit Commutable = 0> - : NeonI_3VSame_HS_sizes -{ + : NeonI_3VSame_HS_sizes { let isCommutable = Commutable in { def _8B : NeonI_3VSame<0b0, u, 0b00, opcode, (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm), @@ -137,8 +134,7 @@ multiclass NeonI_3VSame_BHS_sizes opcode, multiclass NeonI_3VSame_BHSD_sizes opcode, string asmop, SDPatternOperator opnode, bit Commutable = 0> - : NeonI_3VSame_BHS_sizes -{ + : NeonI_3VSame_BHS_sizes { let isCommutable = Commutable in { def _2D : NeonI_3VSame<0b1, u, 0b11, opcode, (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm), @@ -156,8 +152,7 @@ multiclass NeonI_3VSame_SD_sizes opcode, SDPatternOperator opnode4S, SDPatternOperator opnode2D, ValueType ResTy2S, ValueType ResTy4S, - ValueType ResTy2D, bit Commutable = 0> -{ + ValueType ResTy2D, bit Commutable = 0> { let isCommutable = Commutable in { def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode, (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm), @@ -1092,7 +1087,7 @@ multiclass NeonI_mov_imm_lsl_sizes; class NeonI_mov_imm_lsl_aliases - : NeonInstAlias; // Aliases for Vector Move Immediate Shifted @@ -1450,8 +1445,8 @@ def imm0_63 : Operand { let ParserMatchClass = uimm6_asmoperand; } -// Shift Right/Left Immediate - A shift immediate is encoded differently from -// other shift immediates. The immh:immb field is encoded like so: +// Shift Right/Left Immediate - The immh:immb field of these shifts are encoded +// as follows: // // Offset Encoding // 8 immh:immb<6:3> = '0001xxx', is encoded in immh:immb<2:0> @@ -2343,8 +2338,7 @@ defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>; // Variant 3 multiclass NeonI_2VAcross_3 opcode, bits<2> size, - string asmop, SDPatternOperator opnode> -{ + string asmop, SDPatternOperator opnode> { def _1s4s: NeonI_2VAcross<0b1, u, size, opcode, (outs FPR32:$Rd), (ins VPR128:$Rn), asmop # "\t$Rd, $Rn.4s", @@ -2381,8 +2375,7 @@ class NeonI_3VDL size, bits<4> opcode, multiclass NeonI_3VDL_s opcode, string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ + bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, sext, VPR64, v8i16, v8i8>; @@ -2393,10 +2386,8 @@ multiclass NeonI_3VDL_s opcode, } } -multiclass NeonI_3VDL2_s opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL2_s opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b", opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>; @@ -2407,10 +2398,8 @@ multiclass NeonI_3VDL2_s opcode, } } -multiclass NeonI_3VDL_u opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_u opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, zext, VPR64, v8i16, v8i8>; @@ -2421,10 +2410,8 @@ multiclass NeonI_3VDL_u opcode, } } -multiclass NeonI_3VDL2_u opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL2_u opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b", opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>; @@ -2461,9 +2448,8 @@ class NeonI_3VDW size, bits<4> opcode, (ResTy (ext (OpTy OpVPR:$Rm))))))], NoItinerary>; -multiclass NeonI_3VDW_s opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDW_s opcode, string asmop, + SDPatternOperator opnode> { def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, sext, VPR64, v8i16, v8i8>; def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h", @@ -2475,9 +2461,8 @@ multiclass NeonI_3VDW_s opcode, defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>; defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>; -multiclass NeonI_3VDW2_s opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDW2_s opcode, string asmop, + SDPatternOperator opnode> { def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b", opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>; def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h", @@ -2489,9 +2474,8 @@ multiclass NeonI_3VDW2_s opcode, defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>; defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>; -multiclass NeonI_3VDW_u opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDW_u opcode, string asmop, + SDPatternOperator opnode> { def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, zext, VPR64, v8i16, v8i8>; def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h", @@ -2503,9 +2487,8 @@ multiclass NeonI_3VDW_u opcode, defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>; defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>; -multiclass NeonI_3VDW2_u opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDW2_u opcode, string asmop, + SDPatternOperator opnode> { def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b", opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>; def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h", @@ -2518,8 +2501,7 @@ defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>; defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>; // Get the high half part of the vector element. -multiclass NeonI_get_high -{ +multiclass NeonI_get_high { def _8h : PatFrag<(ops node:$Rn), (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn), (v8i16 (Neon_vdup (i32 8)))))))>; @@ -2547,10 +2529,8 @@ class NeonI_3VDN_addhn_2Op size, bits<4> opcode, (OpTy VPR128:$Rm))))))], NoItinerary>; -multiclass NeonI_3VDN_addhn_2Op opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDN_addhn_2Op opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h", opnode, NI_get_hi_8h, v8i8, v8i16>; @@ -2578,10 +2558,8 @@ class NeonI_3VD_2Op size, bits<4> opcode, NoItinerary>; // normal narrow pattern -multiclass NeonI_3VDN_2Op opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDN_2Op opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h", opnode, VPR64, VPR128, v8i8, v8i16>; @@ -2606,8 +2584,7 @@ class NeonI_3VDN_3Op size, bits<4> opcode, let neverHasSideEffects = 1; } -multiclass NeonI_3VDN_3Op_v1 opcode, - string asmop> { +multiclass NeonI_3VDN_3Op_v1 opcode, string asmop> { def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">; def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">; def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">; @@ -2669,10 +2646,8 @@ class NeonI_3VDL_Ext size, bits<4> opcode, (OpTy OpVPR:$Rm))))))], NoItinerary>; -multiclass NeonI_3VDL_zext opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_zext opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, VPR64, v8i16, v8i8, v8i8>; @@ -2686,15 +2661,13 @@ multiclass NeonI_3VDL_zext opcode, defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>; defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>; -multiclass NeonI_Op_High -{ +multiclass NeonI_Op_High { def _16B : PatFrag<(ops node:$Rn, node:$Rm), (op (v8i8 (Neon_High16B node:$Rn)), (v8i8 (Neon_High16B node:$Rm)))>; def _8H : PatFrag<(ops node:$Rn, node:$Rm), (op (v4i16 (Neon_High8H node:$Rn)), (v4i16 (Neon_High8H node:$Rm)))>; def _4S : PatFrag<(ops node:$Rn, node:$Rm), (op (v2i32 (Neon_High4S node:$Rn)), (v2i32 (Neon_High4S node:$Rm)))>; - } defm NI_sabdl_hi : NeonI_Op_High; @@ -2704,10 +2677,8 @@ defm NI_umull_hi : NeonI_Op_High; defm NI_qdmull_hi : NeonI_Op_High; defm NI_pmull_hi : NeonI_Op_High; -multiclass NeonI_3VDL_Abd_u opcode, - string asmop, string opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_Abd_u opcode, string asmop, string opnode, + bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b", !cast(opnode # "_16B"), @@ -2742,10 +2713,8 @@ class NeonI_3VDL_Aba size, bits<4> opcode, let Constraints = "$src = $Rd"; } -multiclass NeonI_3VDL_Aba_v1 opcode, - string asmop, SDPatternOperator opnode, - SDPatternOperator subop> -{ +multiclass NeonI_3VDL_Aba_v1 opcode, string asmop, + SDPatternOperator opnode, SDPatternOperator subop>{ def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, subop, VPR64, v8i16, v8i8, v8i8>; def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h", @@ -2759,10 +2728,8 @@ defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal", defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal", add, int_arm_neon_vabdu>; -multiclass NeonI_3VDL2_Aba_v1 opcode, - string asmop, SDPatternOperator opnode, - string subop> -{ +multiclass NeonI_3VDL2_Aba_v1 opcode, string asmop, + SDPatternOperator opnode, string subop> { def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b", opnode, !cast(subop # "_16B"), VPR128, v8i16, v16i8, v8i8>; @@ -2780,10 +2747,8 @@ defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add, "NI_uabdl_hi">; // Long pattern with 2 operands -multiclass NeonI_3VDL_2Op opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_2Op opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, VPR128, VPR64, v8i16, v8i8>; @@ -2808,12 +2773,8 @@ class NeonI_3VDL2_2Op_mull size, bits<4> opcode, (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))], NoItinerary>; - -multiclass NeonI_3VDL2_2Op_mull_v1 opcode, - string asmop, - string opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL2_2Op_mull_v1 opcode, string asmop, + string opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b", !cast(opnode # "_16B"), @@ -2848,9 +2809,8 @@ class NeonI_3VDL_3Op size, bits<4> opcode, let Constraints = "$src = $Rd"; } -multiclass NeonI_3VDL_3Op_v1 opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDL_3Op_v1 opcode, string asmop, + SDPatternOperator opnode> { def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, v8i16, v8i8>; def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h", @@ -2897,11 +2857,8 @@ class NeonI_3VDL2_3Op_mlas size, bits<4> opcode, let Constraints = "$src = $Rd"; } -multiclass NeonI_3VDL2_3Op_mlas_v1 opcode, - string asmop, - SDPatternOperator subop, - string opnode> -{ +multiclass NeonI_3VDL2_3Op_mlas_v1 opcode, string asmop, + SDPatternOperator subop, string opnode> { def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b", subop, !cast(opnode # "_16B"), VPR128, v8i16, v16i8>; @@ -2923,9 +2880,8 @@ defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2", defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2", sub, "NI_umull_hi">; -multiclass NeonI_3VDL_qdmlal_3Op_v2 opcode, - string asmop, SDPatternOperator opnode> -{ +multiclass NeonI_3VDL_qdmlal_3Op_v2 opcode, string asmop, + SDPatternOperator opnode> { def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h", opnode, int_arm_neon_vqdmull, VPR64, v4i32, v4i16>; @@ -2939,10 +2895,8 @@ defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal", defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl", int_arm_neon_vqsubs>; -multiclass NeonI_3VDL_v2 opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_v2 opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h", opnode, VPR128, VPR64, v4i32, v4i16>; @@ -2954,11 +2908,8 @@ multiclass NeonI_3VDL_v2 opcode, defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull", int_arm_neon_vqdmull, 1>; -multiclass NeonI_3VDL2_2Op_mull_v2 opcode, - string asmop, - string opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL2_2Op_mull_v2 opcode, string asmop, + string opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h", !cast(opnode # "_8H"), @@ -2972,10 +2923,8 @@ multiclass NeonI_3VDL2_2Op_mull_v2 opcode, defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2", "NI_qdmull_hi", 1>; -multiclass NeonI_3VDL2_3Op_qdmlal_v2 opcode, - string asmop, - SDPatternOperator opnode> -{ +multiclass NeonI_3VDL2_3Op_qdmlal_v2 opcode, string asmop, + SDPatternOperator opnode> { def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h", opnode, NI_qdmull_hi_8H, VPR128, v4i32, v8i16>; @@ -2989,10 +2938,8 @@ defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2", defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2", int_arm_neon_vqsubs>; -multiclass NeonI_3VDL_v3 opcode, - string asmop, SDPatternOperator opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL_v3 opcode, string asmop, + SDPatternOperator opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b", opnode, VPR128, VPR64, v8i16, v8i8>; @@ -3001,11 +2948,8 @@ multiclass NeonI_3VDL_v3 opcode, defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>; -multiclass NeonI_3VDL2_2Op_mull_v3 opcode, - string asmop, - string opnode, - bit Commutable = 0> -{ +multiclass NeonI_3VDL2_2Op_mull_v3 opcode, string asmop, + string opnode, bit Commutable = 0> { let isCommutable = Commutable in { def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b", !cast(opnode # "_16B"), @@ -3013,8 +2957,8 @@ multiclass NeonI_3VDL2_2Op_mull_v3 opcode, } } -defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", - "NI_pmull_hi", 1>; +defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi", + 1>; // End of implementation for instruction class (3V Diff) @@ -3149,66 +3093,63 @@ def ST1_4V_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">; class NeonI_Scalar3Same_D_size opcode, string asmop> : NeonI_Scalar3Same; multiclass NeonI_Scalar3Same_HS_sizes opcode, - string asmop, bit Commutable = 0> -{ + string asmop, bit Commutable = 0> { let isCommutable = Commutable in { def hhh : NeonI_Scalar3Same; def sss : NeonI_Scalar3Same; } } multiclass NeonI_Scalar3Same_SD_sizes opcode, - string asmop, bit Commutable = 0> -{ + string asmop, bit Commutable = 0> { let isCommutable = Commutable in { def sss : NeonI_Scalar3Same; def ddd : NeonI_Scalar3Same; } } multiclass NeonI_Scalar3Same_BHSD_sizes opcode, - string asmop, bit Commutable = 0> -{ + string asmop, bit Commutable = 0> { let isCommutable = Commutable in { def bbb : NeonI_Scalar3Same; def hhh : NeonI_Scalar3Same; def sss : NeonI_Scalar3Same; def ddd : NeonI_Scalar3Same; } @@ -3273,12 +3214,12 @@ multiclass Neon_Scalar3Same_cmp_SD_size_patterns opcode, string asmop> { def shh : NeonI_Scalar3Diff; def dss : NeonI_Scalar3Diff; } @@ -3287,12 +3228,12 @@ multiclass NeonI_Scalar3Diff_ml_HS_size opcode, string asmop> { let Constraints = "$Src = $Rd" in { def shh : NeonI_Scalar3Diff; def dss : NeonI_Scalar3Diff; } @@ -3322,18 +3263,18 @@ multiclass NeonI_Scalar2SameMisc_SD_size opcode, string asmop> { def ss : NeonI_Scalar2SameMisc; def dd : NeonI_Scalar2SameMisc; } multiclass NeonI_Scalar2SameMisc_D_size opcode, string asmop> { def dd: NeonI_Scalar2SameMisc; } @@ -3341,15 +3282,15 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size opcode, string asmop> : NeonI_Scalar2SameMisc_D_size { def bb : NeonI_Scalar2SameMisc; def hh : NeonI_Scalar2SameMisc; def ss : NeonI_Scalar2SameMisc; } @@ -3357,15 +3298,15 @@ multiclass NeonI_Scalar2SameMisc_narrow_HSD_size opcode, string asmop> { def bh : NeonI_Scalar2SameMisc; def hs : NeonI_Scalar2SameMisc; def sd : NeonI_Scalar2SameMisc; } @@ -3375,19 +3316,19 @@ multiclass NeonI_Scalar2SameMisc_accum_BHSD_size opcode, let Constraints = "$Src = $Rd" in { def bb : NeonI_Scalar2SameMisc; def hh : NeonI_Scalar2SameMisc; def ss : NeonI_Scalar2SameMisc; def dd: NeonI_Scalar2SameMisc; } } @@ -3414,7 +3355,7 @@ multiclass Neon_Scalar2SameMisc_SD_size_patterns opcode, string asmop> : NeonI_Scalar2SameMisc; @@ -3422,12 +3363,12 @@ multiclass NeonI_Scalar2SameMisc_cmpz_SD_size opcode, string asmop> { def ssi : NeonI_Scalar2SameMisc; def ddi : NeonI_Scalar2SameMisc; } @@ -4118,7 +4059,7 @@ multiclass NeonI_ScalarPair_D_sizes opcode, let isCommutable = Commutable in { def _D_2D : NeonI_ScalarPair; } @@ -4130,7 +4071,7 @@ multiclass NeonI_ScalarPair_SD_sizes opcode, let isCommutable = Commutable in { def _S_2S : NeonI_ScalarPair; } @@ -4374,8 +4315,7 @@ class NI_2VE size, bits<4> opcode, let Constraints = "$src = $Rd"; } -multiclass NI_2VE_v1 opcode, string asmop> -{ +multiclass NI_2VE_v1 opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s", neon_uimm2_bare, VPR64, VPR64, VPR128> { @@ -4492,8 +4432,7 @@ class NI_2VE_2op size, bits<4> opcode, bits<5> Re; } -multiclass NI_2VE_v1_2op opcode, string asmop> -{ +multiclass NI_2VE_v1_2op opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s", neon_uimm2_bare, VPR64, VPR64, VPR128> { @@ -4550,8 +4489,7 @@ class NI_2VE_mul_lane; -multiclass NI_2VE_mul_v1_pat -{ +multiclass NI_2VE_mul_v1_pat { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2i32, v2i32, v4i32, BinOpFrag<(Neon_vduplane @@ -4599,8 +4537,7 @@ defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>; // Variant 2 -multiclass NI_2VE_v2_2op opcode, string asmop> -{ +multiclass NI_2VE_v2_2op opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s", neon_uimm2_bare, VPR64, VPR64, VPR128> { @@ -4638,8 +4575,7 @@ class NI_2VE_mul_lane_2d; -multiclass NI_2VE_mul_v2_pat -{ +multiclass NI_2VE_mul_v2_pat { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v2f32, v4f32, BinOpFrag<(Neon_vduplane @@ -4676,8 +4612,7 @@ defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>; // The followings are patterns using fma // -ffp-contract=fast generates fma -multiclass NI_2VE_v2 opcode, string asmop> -{ +multiclass NI_2VE_v2 opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s", neon_uimm2_bare, VPR64, VPR64, VPR128> { @@ -4737,8 +4672,7 @@ class NI_2VEswap_lane_2d2d; -multiclass NI_2VE_fma_v2_pat -{ +multiclass NI_2VE_fma_v2_pat { def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, BinOpFrag<(Neon_vduplane @@ -4845,8 +4779,7 @@ defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>; // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S -multiclass NI_2VE_v3 opcode, string asmop> -{ +multiclass NI_2VE_v3 opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s", neon_uimm2_bare, VPR128, VPR64, VPR128> { @@ -4887,8 +4820,7 @@ defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">; defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">; defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">; -multiclass NI_2VE_v3_2op opcode, string asmop> -{ +multiclass NI_2VE_v3_2op opcode, string asmop> { // vector register class for element is always 128-bit to cover the max index def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s", neon_uimm2_bare, VPR128, VPR64, VPR128> { @@ -4947,8 +4879,7 @@ class NI_2VEL2_lane; -multiclass NI_2VEL_v3_pat -{ +multiclass NI_2VEL_v3_pat { def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare, op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16, BinOpFrag<(Neon_vduplane @@ -5014,8 +4945,7 @@ class NI_2VEL2_mul_lane; -multiclass NI_2VEL_mul_v3_pat -{ +multiclass NI_2VEL_mul_v3_pat { def : NI_2VE_mul_laneq(subop # "_4s4h"), neon_uimm3_bare, op, VPR64, VPR128Lo, v4i32, v4i16, v8i16, BinOpFrag<(Neon_vduplane @@ -5060,8 +4990,7 @@ defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>; defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>; defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>; -multiclass NI_qdma -{ +multiclass NI_qdma { def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm), (op node:$Ra, (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>; @@ -5074,8 +5003,7 @@ multiclass NI_qdma defm Neon_qdmlal : NI_qdma; defm Neon_qdmlsl : NI_qdma; -multiclass NI_2VEL_v3_qdma_pat -{ +multiclass NI_2VEL_v3_qdma_pat { def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare, !cast(op # "_4s"), VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,