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Enable re-materialization of instructions which have virtual register operands if
the definition of the operand also reaches its uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47475 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
d2b1fb27df
commit
d70dbb5d62
@ -56,6 +56,7 @@ namespace llvm {
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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@ -317,6 +318,18 @@ namespace llvm {
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unsigned MIIdx,
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LiveInterval &interval, bool isAlias = false);
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/// getReMatImplicitUse - If the remat definition MI has one (for now, we
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/// only allow one) virtual register operand, then its uses are implicitly
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/// using the register. Returns the virtual register.
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unsigned getReMatImplicitUse(const LiveInterval &li,
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MachineInstr *MI) const;
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/// isValNoAvailableAt - Return true if the val# of the specified interval
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/// which reaches the given instruction also reaches the specified use
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/// index.
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bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
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unsigned UseIdx) const;
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if the def is a load.
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@ -332,10 +345,11 @@ namespace llvm {
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SmallVector<unsigned, 2> &Ops,
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bool isSS, int Slot, unsigned Reg);
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/// canFoldMemoryOperand - Returns true if the specified load / store
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/// canFoldMemoryOperand - Return true if the specified load / store
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/// folding is possible.
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bool canFoldMemoryOperand(MachineInstr *MI,
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SmallVector<unsigned, 2> &Ops) const;
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bool canFoldMemoryOperand(MachineInstr *MI, unsigned Reg) const;
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/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
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/// VNInfo that's after the specified index but is within the basic block.
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@ -361,26 +375,28 @@ namespace llvm {
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BitVector &RestoreMBBs,
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std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
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/// interval on to-be re-materialized operands of MI) with new register.
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void rewriteImplicitOps(const LiveInterval &li,
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MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
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/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
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/// functions for addIntervalsForSpills to rewrite uses / defs for the given
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/// live range.
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bool rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
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unsigned id, unsigned index, unsigned end, MachineInstr *MI,
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bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
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MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, MachineRegisterInfo &RegMap,
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const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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unsigned &NewVReg, bool &HasDef, bool &HasUse,
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const MachineLoopInfo *loopInfo,
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std::map<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs);
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void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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LiveInterval::Ranges::const_iterator &I,
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MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, MachineRegisterInfo &RegMap,
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const TargetRegisterClass* rc,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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BitVector &SpillMBBs,
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std::map<unsigned,std::vector<SRInfo> > &SpillIdxes,
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@ -83,6 +83,7 @@ void LiveIntervals::releaseMemory() {
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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mri_ = &mf_->getRegInfo();
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tm_ = &fn.getTarget();
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tri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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@ -598,6 +599,38 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
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// Register allocator hooks.
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//
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/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
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/// allow one) virtual register operand, then its uses are implicitly using
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/// the register. Returns the virtual register.
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unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
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MachineInstr *MI) const {
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unsigned RegOp = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || Reg == li.reg)
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continue;
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// FIXME: For now, only remat MI with at most one register operand.
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assert(!RegOp &&
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"Can't rematerialize instruction with multiple register operand!");
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RegOp = MO.getReg();
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break;
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}
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return RegOp;
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}
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/// isValNoAvailableAt - Return true if the val# of the specified interval
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/// which reaches the given instruction also reaches the specified use index.
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bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
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unsigned UseIdx) const {
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unsigned Index = getInstructionIndex(MI);
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VNInfo *ValNo = li.FindLiveRangeContaining(Index)->valno;
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LiveInterval::const_iterator UI = li.FindLiveRangeContaining(UseIdx);
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return UI != li.end() && UI->valno == ValNo;
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}
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable.
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bool LiveIntervals::isReMaterializable(const LiveInterval &li,
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@ -608,8 +641,25 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
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isLoad = false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
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if (TID.isImplicitDef())
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return true;
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if (tii_->isTriviallyReMaterializable(MI)) {
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isLoad = TID.isSimpleLoad();
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unsigned ImpUse = getReMatImplicitUse(li, MI);
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if (ImpUse) {
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const LiveInterval &ImpLi = getInterval(ImpUse);
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for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
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re = mri_->use_end(); ri != re; ++ri) {
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MachineInstr *UseMI = &*ri;
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unsigned UseIdx = getInstructionIndex(UseMI);
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if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
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continue;
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if (!canFoldMemoryOperand(UseMI, li.reg) &&
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!isValNoAvailableAt(ImpLi, MI, UseIdx))
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return false;
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}
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}
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return true;
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}
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@ -654,7 +704,8 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, bool &isLoad) {
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return false;
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MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx);
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bool DefIsLoad = false;
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if (!ReMatDefMI || !isReMaterializable(li, VNI, ReMatDefMI, DefIsLoad))
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if (!ReMatDefMI ||
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!isReMaterializable(li, VNI, ReMatDefMI, DefIsLoad))
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return false;
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isLoad |= DefIsLoad;
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}
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@ -684,14 +735,16 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
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SmallVector<unsigned, 2> FoldOps;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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unsigned OpIdx = Ops[i];
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MachineOperand &MO = MI->getOperand(OpIdx);
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// FIXME: fold subreg use.
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if (MI->getOperand(OpIdx).getSubReg())
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if (MO.getSubReg())
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return false;
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if (MI->getOperand(OpIdx).isDef())
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if (MO.isDef())
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MRInfo |= (unsigned)VirtRegMap::isMod;
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else {
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// Filter out two-address use operand(s).
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if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
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if (!MO.isImplicit() &&
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TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
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MRInfo = VirtRegMap::isModRef;
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continue;
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}
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@ -740,6 +793,23 @@ bool LiveIntervals::canFoldMemoryOperand(MachineInstr *MI,
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return tii_->canFoldMemoryOperand(MI, FoldOps);
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}
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bool LiveIntervals::canFoldMemoryOperand(MachineInstr *MI, unsigned Reg) const {
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SmallVector<unsigned, 2> FoldOps;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& mop = MI->getOperand(i);
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if (!mop.isRegister())
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continue;
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unsigned UseReg = mop.getReg();
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if (UseReg != Reg)
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continue;
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// FIXME: fold subreg use.
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if (mop.getSubReg())
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return false;
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FoldOps.push_back(i);
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}
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return tii_->canFoldMemoryOperand(MI, FoldOps);
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}
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bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
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SmallPtrSet<MachineBasicBlock*, 4> MBBs;
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for (LiveInterval::Ranges::const_iterator
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@ -757,19 +827,43 @@ bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
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return true;
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}
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/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
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/// interval on to-be re-materialized operands of MI) with new register.
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void LiveIntervals::rewriteImplicitOps(const LiveInterval &li,
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MachineInstr *MI, unsigned NewVReg,
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VirtRegMap &vrm) {
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// There is an implicit use. That means one of the other operand is
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// being remat'ed and the remat'ed instruction has li.reg as an
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// use operand. Make sure we rewrite that as well.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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if (!vrm.isReMaterialized(Reg))
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continue;
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MachineInstr *ReMatMI = vrm.getReMaterializedMI(Reg);
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int OpIdx = ReMatMI->findRegisterUseOperandIdx(li.reg);
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if (OpIdx != -1)
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ReMatMI->getOperand(OpIdx).setReg(NewVReg);
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}
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}
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/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper functions
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/// for addIntervalsForSpills to rewrite uses / defs for the given live range.
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bool LiveIntervals::
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rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
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unsigned id, unsigned index, unsigned end, MachineInstr *MI,
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rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
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MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
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unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
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VirtRegMap &vrm,
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const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds,
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unsigned &NewVReg, bool &HasDef, bool &HasUse,
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const MachineLoopInfo *loopInfo,
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unsigned &NewVReg, bool &HasDef, bool &HasUse,
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std::map<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs) {
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bool CanFold = false;
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@ -794,6 +888,14 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
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if (MI == ReMatOrigDefMI && CanDelete) {
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DOUT << "\t\t\t\tErasing re-materlizable def: ";
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DOUT << MI << '\n';
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unsigned ImpUse = getReMatImplicitUse(li, MI);
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if (ImpUse) {
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// To be deleted MI has a virtual register operand, update the
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// spill weight of the register interval.
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unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
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LiveInterval &ImpLi = getInterval(ImpUse);
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ImpLi.weight -= getSpillWeight(false, true, loopDepth);
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}
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RemoveMachineInstrFromMaps(MI);
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vrm.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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@ -862,24 +964,40 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
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// Create a new virtual register for the spill interval.
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bool CreatedNewVReg = false;
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if (NewVReg == 0) {
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NewVReg = RegInfo.createVirtualRegister(rc);
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NewVReg = mri_->createVirtualRegister(rc);
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vrm.grow();
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CreatedNewVReg = true;
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}
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mop.setReg(NewVReg);
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if (mop.isImplicit())
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rewriteImplicitOps(li, MI, NewVReg, vrm);
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// Reuse NewVReg for other reads.
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for (unsigned j = 0, e = Ops.size(); j != e; ++j)
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MI->getOperand(Ops[j]).setReg(NewVReg);
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for (unsigned j = 0, e = Ops.size(); j != e; ++j) {
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MachineOperand &mopj = MI->getOperand(Ops[j]);
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mopj.setReg(NewVReg);
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if (mopj.isImplicit())
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rewriteImplicitOps(li, MI, NewVReg, vrm);
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}
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if (CreatedNewVReg) {
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if (DefIsReMat) {
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unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
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if (ImpUse) {
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// Re-matting an instruction with virtual register use. Add the
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// register as an implicit use on the use MI and update the register
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// interval's spill weight.
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unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
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LiveInterval &ImpLi = getInterval(ImpUse);
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ImpLi.weight += getSpillWeight(false, true, loopDepth);
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MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
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}
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vrm.setVirtIsReMaterialized(NewVReg, ReMatDefMI/*, CanDelete*/);
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if (ReMatIds[id] == VirtRegMap::MAX_STACK_SLOT) {
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if (ReMatIds[VNI->id] == VirtRegMap::MAX_STACK_SLOT) {
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// Each valnum may have its own remat id.
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ReMatIds[id] = vrm.assignVirtReMatId(NewVReg);
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ReMatIds[VNI->id] = vrm.assignVirtReMatId(NewVReg);
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} else {
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vrm.assignVirtReMatId(NewVReg, ReMatIds[id]);
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vrm.assignVirtReMatId(NewVReg, ReMatIds[VNI->id]);
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}
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if (!CanDelete || (HasUse && HasDef)) {
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// If this is a two-addr instruction then its use operands are
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@ -981,7 +1099,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
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unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
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VirtRegMap &vrm,
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const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds,
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const MachineLoopInfo *loopInfo,
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@ -999,8 +1117,8 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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// First collect all the def / use in this live range that will be rewritten.
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// Make sure they are sorted according instruction index.
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std::vector<RewriteInfo> RewriteMIs;
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for (MachineRegisterInfo::reg_iterator ri = RegInfo.reg_begin(li.reg),
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re = RegInfo.reg_end(); ri != re; ) {
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for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
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re = mri_->reg_end(); ri != re; ) {
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MachineInstr *MI = &(*ri);
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MachineOperand &O = ri.getOperand();
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++ri;
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@ -1063,11 +1181,11 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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bool HasDef = false;
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bool HasUse = false;
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bool CanFold = rewriteInstructionForSpills(li, TrySplit, I->valno->id,
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bool CanFold = rewriteInstructionForSpills(li, I->valno, TrySplit,
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index, end, MI, ReMatOrigDefMI, ReMatDefMI,
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Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
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CanDelete, vrm, RegInfo, rc, ReMatIds, NewVReg,
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HasDef, HasUse, loopInfo, MBBVRegsMap, NewLIs);
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CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
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HasDef, HasUse, MBBVRegsMap, NewLIs);
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if (!HasDef && !HasUse)
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continue;
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@ -1211,8 +1329,7 @@ addIntervalsForSpills(const LiveInterval &li,
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std::map<unsigned, std::vector<SRInfo> > RestoreIdxes;
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std::map<unsigned,unsigned> MBBVRegsMap;
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std::vector<LiveInterval*> NewLIs;
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MachineRegisterInfo &RegInfo = mf_->getRegInfo();
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const TargetRegisterClass* rc = RegInfo.getRegClass(li.reg);
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const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
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unsigned NumValNums = li.getNumValNums();
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SmallVector<MachineInstr*, 4> ReMatDefs;
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@ -1257,13 +1374,13 @@ addIntervalsForSpills(const LiveInterval &li,
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// Note ReMatOrigDefMI has already been deleted.
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rewriteInstructionsForSpills(li, false, I, NULL, ReMatDefMI,
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Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
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false, vrm, RegInfo, rc, ReMatIds, loopInfo,
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false, vrm, rc, ReMatIds, loopInfo,
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SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
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MBBVRegsMap, NewLIs);
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} else {
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rewriteInstructionsForSpills(li, false, I, NULL, 0,
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Slot, 0, false, false, false,
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false, vrm, RegInfo, rc, ReMatIds, loopInfo,
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false, vrm, rc, ReMatIds, loopInfo,
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SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
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MBBVRegsMap, NewLIs);
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}
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@ -1331,7 +1448,7 @@ addIntervalsForSpills(const LiveInterval &li,
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(DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
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rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
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Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
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CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
|
||||
CanDelete, vrm, rc, ReMatIds, loopInfo,
|
||||
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
|
||||
MBBVRegsMap, NewLIs);
|
||||
}
|
||||
@ -1446,6 +1563,16 @@ addIntervalsForSpills(const LiveInterval &li,
|
||||
if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
|
||||
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
|
||||
Ops, isLoadSS, LdSlot, VReg);
|
||||
unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
|
||||
if (ImpUse) {
|
||||
// Re-matting an instruction with virtual register use. Add the
|
||||
// register as an implicit use on the use MI and update the register
|
||||
// interval's spill weight.
|
||||
unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
|
||||
LiveInterval &ImpLi = getInterval(ImpUse);
|
||||
ImpLi.weight += getSpillWeight(false, true, loopDepth);
|
||||
MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
|
||||
}
|
||||
}
|
||||
}
|
||||
// If folding is not possible / failed, then tell the spiller to issue a
|
||||
@ -1471,8 +1598,8 @@ addIntervalsForSpills(const LiveInterval &li,
|
||||
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
|
||||
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
|
||||
assert(UseIdx != -1);
|
||||
if (LastUse->getDesc().getOperandConstraint(UseIdx, TOI::TIED_TO) ==
|
||||
-1) {
|
||||
if (LastUse->getOperand(UseIdx).isImplicit() ||
|
||||
LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){
|
||||
LastUse->getOperand(UseIdx).setIsKill();
|
||||
vrm.addKillPoint(LI->reg, LastUseIdx);
|
||||
}
|
||||
|
||||
@ -574,6 +574,32 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
|
||||
}
|
||||
}
|
||||
|
||||
/// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
|
||||
///
|
||||
static void ReMaterialize(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MII,
|
||||
unsigned DestReg, unsigned Reg,
|
||||
const TargetRegisterInfo *TRI,
|
||||
VirtRegMap &VRM) {
|
||||
TRI->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
|
||||
MachineInstr *NewMI = prior(MII);
|
||||
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = NewMI->getOperand(i);
|
||||
if (!MO.isRegister() || MO.getReg() == 0)
|
||||
continue;
|
||||
unsigned VirtReg = MO.getReg();
|
||||
if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
|
||||
continue;
|
||||
assert(MO.isUse());
|
||||
unsigned SubIdx = MO.getSubReg();
|
||||
unsigned Phys = VRM.getPhys(VirtReg);
|
||||
assert(Phys);
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
|
||||
MO.setReg(RReg);
|
||||
}
|
||||
++NumReMats;
|
||||
}
|
||||
|
||||
|
||||
// ReusedOp - For each reused operand, we keep track of a bit of information, in
|
||||
// case we need to rollback upon processing a new operand. See comments below.
|
||||
@ -693,12 +719,11 @@ namespace {
|
||||
MI, Spills, MaybeDeadStores,
|
||||
Rejected, RegKills, KillOps, VRM);
|
||||
|
||||
MachineBasicBlock::iterator MII = MI;
|
||||
if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
|
||||
TRI->reMaterialize(*MBB, MI, NewPhysReg,
|
||||
VRM.getReMaterializedMI(NewOp.VirtReg));
|
||||
++NumReMats;
|
||||
ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TRI, VRM);
|
||||
} else {
|
||||
TII->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
|
||||
TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
|
||||
NewOp.StackSlotOrReMat, AliasRC);
|
||||
// Any stores to this stack slot are not dead anymore.
|
||||
MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
|
||||
@ -710,7 +735,6 @@ namespace {
|
||||
MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
|
||||
|
||||
Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
|
||||
MachineBasicBlock::iterator MII = MI;
|
||||
--MII;
|
||||
UpdateKills(*MII, RegKills, KillOps);
|
||||
DOUT << '\t' << *MII;
|
||||
@ -973,15 +997,13 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
if (VRM.isRestorePt(&MI)) {
|
||||
std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
|
||||
for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
|
||||
unsigned VirtReg = RestoreRegs[i];
|
||||
unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
|
||||
if (!VRM.getPreSplitReg(VirtReg))
|
||||
continue; // Split interval spilled again.
|
||||
unsigned Phys = VRM.getPhys(VirtReg);
|
||||
RegInfo->setPhysRegUsed(Phys);
|
||||
if (VRM.isReMaterialized(VirtReg)) {
|
||||
TRI->reMaterialize(MBB, &MI, Phys,
|
||||
VRM.getReMaterializedMI(VirtReg));
|
||||
++NumReMats;
|
||||
ReMaterialize(MBB, MII, Phys, VirtReg, TRI, VRM);
|
||||
} else {
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
|
||||
@ -1219,8 +1241,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||
RegInfo->setPhysRegUsed(PhysReg);
|
||||
ReusedOperands.markClobbered(PhysReg);
|
||||
if (DoReMat) {
|
||||
TRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
|
||||
++NumReMats;
|
||||
ReMaterialize(MBB, MII, PhysReg, VirtReg, TRI, VRM);
|
||||
} else {
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user