6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-04 10:30:01 +00:00
Code Issues Projects Releases Wiki Activity

Allow FastISel of three-register-operand instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130934 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-05-05 17:59:04 +00:00
parent d96efb83c1
commit d71867a8f4
2 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
include/llvm/CodeGen/FastISel.h
View File

@ -241,6 +241,15 @@ protected:
unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill);
/// FastEmitInst_rrr - Emit a MachineInstr with three register operands
/// and a result register in the given register class.
///
unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill,
unsigned Op2, bool Op2IsKill);
/// FastEmitInst_ri - Emit a MachineInstr with a register operand,
/// an immediate, and a result register in the given register class.
///

24
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -1097,6 +1097,30 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
return ResultReg;
}
unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill,
unsigned Op2, bool Op2IsKill) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
.addReg(Op0, Op0IsKill * RegState::Kill)
.addReg(Op1, Op1IsKill * RegState::Kill)
.addReg(Op2, Op2IsKill * RegState::Kill);
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
.addReg(Op0, Op0IsKill * RegState::Kill)
.addReg(Op1, Op1IsKill * RegState::Kill)
.addReg(Op2, Op2IsKill * RegState::Kill);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
ResultReg).addReg(II.ImplicitDefs[0]);
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill,