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Support returning non-power-of-2 vectors to unblock some work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44371 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -364,6 +364,13 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
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unsigned NumVectorRegs = 1;
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// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
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// could break down into LHS/RHS like LegalizeDAG does.
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if (!isPowerOf2_32(NumElts)) {
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NumVectorRegs = NumElts;
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NumElts = 1;
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}
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 &&
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@ -52,10 +52,12 @@ def RetCC_X86_32_C : CallingConv<[
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// X86-32 FastCC return-value convention.
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def RetCC_X86_32_Fast : CallingConv<[
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// The X86-32 fastcc returns FP values in XMM0 if the target has SSE2,
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// otherwise it is the the C calling conventions.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
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// The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
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// SSE2, otherwise it is the the C calling conventions.
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// This can happen when a float, 2 x float, or 3 x float vector is split by
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// target lowering, and is returned in 1-3 sse regs.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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