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Use symbolic operands in the patchpoint folding routine and fix a spilling bug.

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Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195094 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-11-19 03:29:59 +00:00
parent 8ddf988ef4
commit d73d4f4ef2
2 changed files with 47 additions and 9 deletions
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14
lib/Target/X86/X86InstrInfo.cpp
View File

@ -4203,19 +4203,17 @@ static MachineInstr* foldPatchpoint(MachineFunction &MF,
const SmallVectorImpl<unsigned> &Ops, const SmallVectorImpl<unsigned> &Ops,
int FrameIndex, int FrameIndex,
const TargetInstrInfo &TII) { const TargetInstrInfo &TII) {
bool hasDef = MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && unsigned StartIdx = 0;
!MI->getOperand(0).isImplicit();
unsigned StartIdx = hasDef ? 1 : 0;
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case TargetOpcode::STACKMAP: case TargetOpcode::STACKMAP:
StartIdx += 2; // Skip ID, nShadowBytes. StartIdx = 2; // Skip ID, nShadowBytes.
break; break;
case TargetOpcode::PATCHPOINT: case TargetOpcode::PATCHPOINT: {
// Skip ID, numBytes, Target, numArgs.
// For PatchPoint, the call args are not foldable. // For PatchPoint, the call args are not foldable.
StartIdx += MI->getOperand(StartIdx+3).getImm() + 4; PatchPointOpers opers(MI);
StartIdx = opers.getVarIdx();
break; break;
}
default: default:
llvm_unreachable("unexpected stackmap opcode"); llvm_unreachable("unexpected stackmap opcode");
} }

42
test/CodeGen/X86/anyregcc.ll
View File

@ -8,7 +8,7 @@
; Num Constants ; Num Constants
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; Num Callsites ; Num Callsites
; CHECK-NEXT: .long 7 ; CHECK-NEXT: .long 8
; test ; test
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
@ -304,5 +304,45 @@ entry:
ret i64 %result ret i64 %result
} }
; Test spilling the arguments of an anyregcc call.
;
; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
;
; CHECK-LABEL: .long 13
; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 5
; Loc 0: Return a register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .short {{[0-9]+}}
; CHECK-NEXT: .long 0
; Loc 1: Arg0 in a Register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .short {{[0-9]+}}
; CHECK-NEXT: .long 0
; Loc 2: Arg1 in a Register
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .short {{[0-9]+}}
; CHECK-NEXT: .long 0
; Loc 3: Arg2 spilled to RBP +
; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .short 7
; CHECK-NEXT: .long {{[0-9]+}}
; Loc 4: Arg3 spilled to RBP +
; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .short 7
; CHECK-NEXT: .long {{[0-9]+}}
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
%result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
ret i64 %result
}
declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...) declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...) declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)