From d7433e2873706265d545edc5cdd0a728dd71ef66 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 23 Jan 2012 23:45:44 +0000 Subject: [PATCH] NEON VST3(multiple 3-element structures) assembly parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrNEON.td | 59 ++++++++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 167 +++++++++++++++++++--- test/MC/ARM/neon-vst-encoding.s | 56 +++++--- 3 files changed, 244 insertions(+), 38 deletions(-) diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index f5cd2a89747..acb7453ddcb 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -6085,6 +6085,65 @@ def VLD3qWB_register_Asm_32 : (ins VecListThreeQ:$list, addrmode6:$addr, rGPR:$Rm, pred:$p)>; +// VST3 multiple structurepseudo-instructions. These need special handling for +// the vector operands that the normal instructions don't yet model. +// FIXME: Remove these when the register classes and instructions are updated. +def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; +def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; +def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; + +def VST3dWB_fixed_Asm_8 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3dWB_fixed_Asm_16 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3dWB_fixed_Asm_32 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", + (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; +def VST3qWB_fixed_Asm_8 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; +def VST3qWB_fixed_Asm_16 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; +def VST3qWB_fixed_Asm_32 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", + (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; +def VST3dWB_register_Asm_8 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", + (ins VecListThreeD:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +def VST3dWB_register_Asm_16 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", + (ins VecListThreeD:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +def VST3dWB_register_Asm_32 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", + (ins VecListThreeD:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +def VST3qWB_register_Asm_8 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", + (ins VecListThreeQ:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +def VST3qWB_register_Asm_16 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", + (ins VecListThreeQ:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; +def VST3qWB_register_Asm_32 : + NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", + (ins VecListThreeQ:$list, addrmode6:$addr, + rGPR:$Rm, pred:$p)>; + // VMOV takes an optional datatype suffix diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 37c761b4b80..01c3c6dc5aa 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5173,7 +5173,7 @@ validateInstruction(MCInst &Inst, return false; } -static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { +static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VST1LN @@ -5253,10 +5253,66 @@ static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) { case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; + + // VST3 + case ARM::VST3dWB_fixed_Asm_8: + Spacing = 1; + return ARM::VST3d8_UPD; + case ARM::VST3dWB_fixed_Asm_16: + Spacing = 1; + return ARM::VST3d16_UPD; + case ARM::VST3dWB_fixed_Asm_32: + Spacing = 1; + return ARM::VST3d32_UPD; + case ARM::VST3qWB_fixed_Asm_8: + Spacing = 2; + return ARM::VST3q8_UPD; + case ARM::VST3qWB_fixed_Asm_16: + Spacing = 2; + return ARM::VST3q16_UPD; + case ARM::VST3qWB_fixed_Asm_32: + Spacing = 2; + return ARM::VST3q32_UPD; + case ARM::VST3dWB_register_Asm_8: + Spacing = 1; + return ARM::VST3d8_UPD; + case ARM::VST3dWB_register_Asm_16: + Spacing = 1; + return ARM::VST3d16_UPD; + case ARM::VST3dWB_register_Asm_32: + Spacing = 1; + return ARM::VST3d32_UPD; + case ARM::VST3qWB_register_Asm_8: + Spacing = 2; + return ARM::VST3q8_UPD; + case ARM::VST3qWB_register_Asm_16: + Spacing = 2; + return ARM::VST3q16_UPD; + case ARM::VST3qWB_register_Asm_32: + Spacing = 2; + return ARM::VST3q32_UPD; + case ARM::VST3dAsm_8: + Spacing = 1; + return ARM::VST3d8; + case ARM::VST3dAsm_16: + Spacing = 1; + return ARM::VST3d16; + case ARM::VST3dAsm_32: + Spacing = 1; + return ARM::VST3d32; + case ARM::VST3qAsm_8: + Spacing = 2; + return ARM::VST3q8; + case ARM::VST3qAsm_16: + Spacing = 2; + return ARM::VST3q16; + case ARM::VST3qAsm_32: + Spacing = 2; + return ARM::VST3q32; } } -static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) { +static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { switch(Opc) { default: assert(0 && "unexpected opcode!"); // VLD1LN @@ -5468,7 +5524,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5490,7 +5546,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5511,7 +5567,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5533,7 +5589,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5554,7 +5610,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd @@ -5574,7 +5630,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment TmpInst.addOperand(Inst.getOperand(0)); // Vd @@ -5594,7 +5650,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5617,7 +5673,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5644,7 +5700,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5673,7 +5729,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb TmpInst.addOperand(Inst.getOperand(2)); // Rn @@ -5696,7 +5752,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5723,7 +5779,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5752,7 +5808,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(Inst.getOperand(2)); // Rn TmpInst.addOperand(Inst.getOperand(3)); // alignment @@ -5773,7 +5829,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5798,7 +5854,7 @@ processInstruction(MCInst &Inst, // Shuffle the operands around so the lane index operand is in the // right place. unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5827,7 +5883,7 @@ processInstruction(MCInst &Inst, case ARM::VLD3qAsm_32: { MCInst TmpInst; unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5849,7 +5905,7 @@ processInstruction(MCInst &Inst, case ARM::VLD3qWB_fixed_Asm_32: { MCInst TmpInst; unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5873,7 +5929,7 @@ processInstruction(MCInst &Inst, case ARM::VLD3qWB_register_Asm_32: { MCInst TmpInst; unsigned Spacing; - TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing)); + TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); TmpInst.addOperand(Inst.getOperand(0)); // Vd TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + Spacing)); @@ -5889,6 +5945,77 @@ processInstruction(MCInst &Inst, return true; } + // VST3 multiple 3-element structure instructions. + case ARM::VST3dAsm_8: + case ARM::VST3dAsm_16: + case ARM::VST3dAsm_32: + case ARM::VST3qAsm_8: + case ARM::VST3qAsm_16: + case ARM::VST3qAsm_32: { + MCInst TmpInst; + unsigned Spacing; + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(Inst.getOperand(2)); // alignment + TmpInst.addOperand(Inst.getOperand(0)); // Vd + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing * 2)); + TmpInst.addOperand(Inst.getOperand(3)); // CondCode + TmpInst.addOperand(Inst.getOperand(4)); + Inst = TmpInst; + return true; + } + + case ARM::VST3dWB_fixed_Asm_8: + case ARM::VST3dWB_fixed_Asm_16: + case ARM::VST3dWB_fixed_Asm_32: + case ARM::VST3qWB_fixed_Asm_8: + case ARM::VST3qWB_fixed_Asm_16: + case ARM::VST3qWB_fixed_Asm_32: { + MCInst TmpInst; + unsigned Spacing; + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn + TmpInst.addOperand(Inst.getOperand(2)); // alignment + TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm + TmpInst.addOperand(Inst.getOperand(0)); // Vd + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing * 2)); + TmpInst.addOperand(Inst.getOperand(3)); // CondCode + TmpInst.addOperand(Inst.getOperand(4)); + Inst = TmpInst; + return true; + } + + case ARM::VST3dWB_register_Asm_8: + case ARM::VST3dWB_register_Asm_16: + case ARM::VST3dWB_register_Asm_32: + case ARM::VST3qWB_register_Asm_8: + case ARM::VST3qWB_register_Asm_16: + case ARM::VST3qWB_register_Asm_32: { + MCInst TmpInst; + unsigned Spacing; + TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn + TmpInst.addOperand(Inst.getOperand(2)); // alignment + TmpInst.addOperand(Inst.getOperand(3)); // Rm + TmpInst.addOperand(Inst.getOperand(0)); // Vd + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing)); + TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + + Spacing * 2)); + TmpInst.addOperand(Inst.getOperand(4)); // CondCode + TmpInst.addOperand(Inst.getOperand(5)); + Inst = TmpInst; + return true; + } + // Handle the Thumb2 mode MOV complex aliases. case ARM::t2MOVsr: case ARM::t2MOVSsr: { diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index 9dd85347f27..79e74f58709 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -58,25 +58,45 @@ @ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4] -@ vst3.8 {d16, d17, d18}, [r0, :64] -@ vst3.16 {d16, d17, d18}, [r0] -@ vst3.32 {d16, d17, d18}, [r0] -@ vst3.8 {d16, d18, d20}, [r0, :64]! -@ vst3.8 {d17, d19, d21}, [r0, :64]! -@ vst3.16 {d16, d18, d20}, [r0]! -@ vst3.16 {d17, d19, d21}, [r0]! -@ vst3.32 {d16, d18, d20}, [r0]! -@ vst3.32 {d17, d19, d21}, [r0]! + vst3.8 {d16, d17, d18}, [r1] + vst3.16 {d6, d7, d8}, [r2] + vst3.32 {d1, d2, d3}, [r3] + vst3.8 {d16, d18, d20}, [r0, :64] + vst3.u16 {d27, d29, d31}, [r4] + vst3.i32 {d6, d8, d10}, [r5] -@ FIXME: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4] -@ FIXME: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4] -@ FIXME: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4] -@ FIXME: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] -@ FIXME: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4] -@ FIXME: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4] -@ FIXME: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4] -@ FIXME: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4] -@ FIXME: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4] + vst3.i8 {d12, d13, d14}, [r6], r1 + vst3.i16 {d11, d12, d13}, [r7], r2 + vst3.u32 {d2, d3, d4}, [r8], r3 + vst3.8 {d4, d6, d8}, [r9], r4 + vst3.u16 {d14, d16, d18}, [r9], r4 + vst3.i32 {d16, d18, d20}, [r10], r5 + + vst3.p8 {d6, d7, d8}, [r8]! + vst3.16 {d9, d10, d11}, [r7]! + vst3.f32 {d1, d2, d3}, [r6]! + vst3.8 {d16, d18, d20}, [r0, :64]! + vst3.p16 {d20, d22, d24}, [r5]! + vst3.32 {d5, d7, d9}, [r4]! + +@ CHECK: vst3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x41,0xf4] +@ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4] +@ CHECK: vst3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x03,0xf4] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x40,0xf4] +@ CHECK: vst3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x44,0xf4] +@ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4] +@ CHECK: vst3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x06,0xf4] +@ CHECK: vst3.16 {d11, d12, d13}, [r7], r2 @ encoding: [0x42,0xb4,0x07,0xf4] +@ CHECK: vst3.32 {d2, d3, d4}, [r8], r3 @ encoding: [0x83,0x24,0x08,0xf4] +@ CHECK: vst3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x09,0xf4] +@ CHECK: vst3.16 {d14, d16, d18}, [r9], r4 @ encoding: [0x44,0xe5,0x09,0xf4] +@ CHECK: vst3.32 {d16, d18, d20}, [r10], r5 @ encoding: [0x85,0x05,0x4a,0xf4] +@ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4] +@ CHECK: vst3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x07,0xf4] +@ CHECK: vst3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x06,0xf4] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] +@ CHECK: vst3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x45,0xf4] +@ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4] @ vst4.8 {d16, d17, d18, d19}, [r0, :64]