From d74434656619d19e3e5c3dec79c6ccdaef567bec Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Thu, 15 May 2014 11:16:19 +0000 Subject: [PATCH] ARM64: add correct vector registers during asm parsing Previously, we ignored the difference between V64 and V128 when parsing assembly: they both got mapped to registers in the FPR128 class. This is basically harmless at the moment because they both print and encode the same way. However, it will affect the printing of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208866 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64RegisterInfo.td | 19 +++++++++++++++---- lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 9 ++++++++- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/lib/Target/ARM64/ARM64RegisterInfo.td b/lib/Target/ARM64/ARM64RegisterInfo.td index c6ce671d56f..fb82598ff7a 100644 --- a/lib/Target/ARM64/ARM64RegisterInfo.td +++ b/lib/Target/ARM64/ARM64RegisterInfo.td @@ -434,10 +434,21 @@ def QQQQ : RegisterClass<"ARM64", [untyped], 128, (add QSeqQuads)> { // Vector operand versions of the FP registers. Alternate name printing and // assmebler matching. -def VectorRegAsmOperand : AsmOperandClass { let Name = "VectorReg"; } -let ParserMatchClass = VectorRegAsmOperand in { -def V64 : RegisterOperand; -def V128 : RegisterOperand; +def VectorReg64AsmOperand : AsmOperandClass { + let Name = "VectorReg64"; + let PredicateMethod = "isVectorReg"; +} +def VectorReg128AsmOperand : AsmOperandClass { + let Name = "VectorReg128"; + let PredicateMethod = "isVectorReg"; +} + +def V64 : RegisterOperand { + let ParserMatchClass = VectorReg64AsmOperand; +} + +def V128 : RegisterOperand { + let ParserMatchClass = VectorReg128AsmOperand; } def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; } diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index a68f4db633a..d95a51167d5 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -1188,8 +1188,15 @@ public: Inst.addOperand(MCOperand::CreateReg(getReg())); } - void addVectorRegOperands(MCInst &Inst, unsigned N) const { + void addVectorReg64Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); + assert(ARM64MCRegisterClasses[ARM64::FPR128RegClassID].contains(getReg())); + Inst.addOperand(MCOperand::CreateReg(ARM64::D0 + getReg() - ARM64::Q0)); + } + + void addVectorReg128Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + assert(ARM64MCRegisterClasses[ARM64::FPR128RegClassID].contains(getReg())); Inst.addOperand(MCOperand::CreateReg(getReg())); }