From d770d9e7d1f5c65b185897dcf226b3fc64598683 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 2 Jul 2009 06:38:40 +0000 Subject: [PATCH] Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 8 ++++---- lib/Target/ARM/ARMInstrInfo.td | 2 +- lib/Target/ARM/ARMInstrThumb2.td | 20 ++++++++++---------- lib/Target/ARM/ARMSubtarget.h | 3 ++- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 072e9a260e7..d7b02c3a4ec 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -823,7 +823,7 @@ class Thumb2I Predicates = [IsThumb, HasThumb2]; + list Predicates = [IsThumb2]; } // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as @@ -838,7 +838,7 @@ class Thumb2sI Predicates = [IsThumb, HasThumb2]; + list Predicates = [IsThumb2]; } // Special cases @@ -849,7 +849,7 @@ class Thumb2XI Predicates = [IsThumb, HasThumb2]; + list Predicates = [IsThumb2]; } class T2I pattern> @@ -875,7 +875,7 @@ class T2JTI pattern> // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. class T2Pat : Pat { - list Predicates = [IsThumb, HasThumb2]; + list Predicates = [IsThumb2]; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 496fdc491e2..408f47a6e10 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -99,7 +99,7 @@ def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; def HasNEON : Predicate<"Subtarget->hasNEON()">; def IsThumb : Predicate<"Subtarget->isThumb()">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; -def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; +def IsThumb2 : Predicate<"Subtarget->isThumb2()">; def IsARM : Predicate<"!Subtarget->isThumb()">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index e135c8153a5..526c31286fb 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -270,32 +270,32 @@ multiclass T2I_adde_sube_irs { def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), opc, " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>; + Requires<[IsThumb2, CarryDefIsUnused]>; // register def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), opc, " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUnused]> { + Requires<[IsThumb2, CarryDefIsUnused]> { let isCommutable = Commutable; } // shifted register def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), opc, " $dst, $lhs, $rhs", [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>; + Requires<[IsThumb2, CarryDefIsUnused]>; // Carry setting variants // shifted imm def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> { + Requires<[IsThumb2, CarryDefIsUsed]> { let Defs = [CPSR]; } // register def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> { + Requires<[IsThumb2, CarryDefIsUsed]> { let Defs = [CPSR]; let isCommutable = Commutable; } @@ -303,7 +303,7 @@ multiclass T2I_adde_sube_irs { def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), !strconcat(opc, "s $dst, $lhs, $rhs"), [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> { + Requires<[IsThumb2, CarryDefIsUsed]> { let Defs = [CPSR]; } } @@ -318,24 +318,24 @@ multiclass T2I_rsc_is { def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>; + Requires<[IsThumb2, CarryDefIsUnused]>; // shifted register def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), opc, " $dst, $rhs, $lhs", [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUnused]>; + Requires<[IsThumb2, CarryDefIsUnused]>; // shifted imm def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> { + Requires<[IsThumb2, CarryDefIsUsed]> { let Defs = [CPSR]; } // shifted register def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), !strconcat(opc, "s $dst, $rhs, $lhs"), [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>, - Requires<[IsThumb, HasThumb2, CarryDefIsUsed]> { + Requires<[IsThumb2, CarryDefIsUsed]> { let Defs = [CPSR]; } } diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index c3cc7fff6e3..5110b3157c4 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -108,7 +108,8 @@ protected: bool isThumb() const { return IsThumb; } bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } - bool hasThumb2() const { return IsThumb && (ThumbMode >= Thumb2); } + bool isThumb2() const { return IsThumb && (ThumbMode >= Thumb2); } + bool hasThumb2() const { return ThumbMode >= Thumb2; } bool isR9Reserved() const { return IsR9Reserved; }