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Simplify code a bit. No functional change intended.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-04-29 20:22:05 +00:00
parent a04fe83378
commit d77d2feb7a
1 changed files with 3 additions and 4 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
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@ -6956,14 +6956,13 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
}
if (Op.getValueType() == MVT::v1i64 &&
if (OpVT == MVT::v1i64 &&
Op.getOperand(0).getValueType() == MVT::i64)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
"Expected an SSE type!");
return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
return DAG.getNode(ISD::BITCAST, dl, OpVT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
}