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cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -705,28 +705,26 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
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Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
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if (Opc) {
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineInstrBuilder Mov;
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for (unsigned i = 0; i != SubRegs; ++i) {
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unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
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unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
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assert(Dst && Src && "Bad sub-register");
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Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
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.addReg(Src);
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// VORR takes two source operands.
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if (Opc == ARM::VORRq)
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Mov.addReg(Src);
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Mov = AddDefaultPred(Mov);
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}
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// Add implicit super-register defs and kills to the last instruction.
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Mov->addRegisterDefined(DestReg, TRI);
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if (KillSrc)
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Mov->addRegisterKilled(SrcReg, TRI);
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return;
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}
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if (!Opc)
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llvm_unreachable("Impossible reg-to-reg copy");
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llvm_unreachable("Impossible reg-to-reg copy");
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineInstrBuilder Mov;
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for (unsigned i = 0; i != SubRegs; ++i) {
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unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
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unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
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assert(Dst && Src && "Bad sub-register");
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Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
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.addReg(Src);
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// VORR takes two source operands.
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if (Opc == ARM::VORRq)
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Mov.addReg(Src);
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Mov = AddDefaultPred(Mov);
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}
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// Add implicit super-register defs and kills to the last instruction.
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Mov->addRegisterDefined(DestReg, TRI);
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if (KillSrc)
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Mov->addRegisterKilled(SrcReg, TRI);
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}
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static const
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