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R600: Expand vector FNEG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,6 +78,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::LOAD, MVT::f64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
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setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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26
test/CodeGen/R600/fneg.ll
Normal file
26
test/CodeGen/R600/fneg.ll
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@ -0,0 +1,26 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; XXX: There is a bug in the DAGCombiner that lowers fneg to XOR, this test
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; will need to be changed once it is fixed.
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; CHECK: @fneg_v2
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; CHECK: XOR_INT
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; CHECK: XOR_INT
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define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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entry:
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%0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; CHECK: @fneg_v4
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; CHECK: XOR_INT
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; CHECK: XOR_INT
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; CHECK: XOR_INT
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; CHECK: XOR_INT
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define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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entry:
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%0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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store <4 x float> %0, <4 x float> addrspace(1)* %out
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ret void
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}
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