diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index e49fdfbee6b..f6548458840 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1149,7 +1149,7 @@ void ISel::Select(SDOperand N) {
     Tmp2 = SelectExpr(N.getOperand(2));
 
     switch (StoredTy) {
-    default: Node->dump(); assert(0 && "Unhandled Type"); break;
+    default: Node->dump(); assert(0 && "Unhandled Type");
     case MVT::i1: //FIXME: DAG does not promote this load
     case MVT::i8: Opc = Alpha::STB; break;
     case MVT::i16: Opc = Alpha::STW; break;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index a35c210d20d..7e6c5d38f35 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -108,7 +108,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
       Amount = (Amount+Align-1)/Align*Align;
 
-      MachineInstr *New;
+//    MachineInstr *New;
 //       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
 // 	New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
 //               .addZImm(Amount);