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Mark the instructions that have delay slots with the hasDelaySlot flag.
Add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16611 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -47,9 +47,9 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
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def RET : F3_2<2, 0b111000, "ret">;
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, "retl">;
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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@ -148,6 +148,7 @@ def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
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class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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let isBarrier = 1 in
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@ -170,6 +171,7 @@ def BCS : BranchV8<0b0101, "bcs">;
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class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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def FBA : FPBranchV8<0b1000, "fba">;
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@ -191,14 +193,15 @@ def FBO : FPBranchV8<0b1111, "fbo">;
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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let Defs = [O0, O1, O2, O3, O4, O5] in
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let isCall = 1 in {
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let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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// pc-relative call:
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def CALL : InstV8 {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let Name = "call";
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}
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// indirect call:
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def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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}
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@ -233,9 +236,14 @@ def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
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def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
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// Floating-point Compare Instructions, p. 148
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// Note: the 2nd template arg is different for these guys
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def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
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// Note: the 2nd template arg is different for these guys.
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// Note 2: the result of a FCMP is not available until the 2nd cycle
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// after the instr is retired, but there is no interlock. This behavior
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// is modelled as a delay slot.
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let hasDelaySlot = 1 in {
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def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
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}
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@ -47,9 +47,9 @@ def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
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def RET : F3_2<2, 0b111000, "ret">;
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, "retl">;
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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@ -148,6 +148,7 @@ def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
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class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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let isBarrier = 1 in
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@ -170,6 +171,7 @@ def BCS : BranchV8<0b0101, "bcs">;
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class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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def FBA : FPBranchV8<0b1000, "fba">;
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@ -191,14 +193,15 @@ def FBO : FPBranchV8<0b1111, "fbo">;
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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let Defs = [O0, O1, O2, O3, O4, O5] in
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let isCall = 1 in {
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let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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// pc-relative call:
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def CALL : InstV8 {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let Name = "call";
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}
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// indirect call:
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def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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}
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@ -233,9 +236,14 @@ def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
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def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
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// Floating-point Compare Instructions, p. 148
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// Note: the 2nd template arg is different for these guys
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def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
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// Note: the 2nd template arg is different for these guys.
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// Note 2: the result of a FCMP is not available until the 2nd cycle
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// after the instr is retired, but there is no interlock. This behavior
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// is modelled as a delay slot.
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let hasDelaySlot = 1 in {
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def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
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}
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