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Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative
value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1055,8 +1055,7 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const {
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int Opcode = MI0->getOpcode();
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if (Opcode == ARM::LDRi12 ||
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Opcode == ARM::t2LDRpci ||
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if (Opcode == ARM::t2LDRpci ||
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Opcode == ARM::t2LDRpci_pic ||
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Opcode == ARM::tLDRpci ||
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Opcode == ARM::tLDRpci_pic ||
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@ -1069,9 +1068,6 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
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const MachineOperand &MO0 = MI0->getOperand(1);
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const MachineOperand &MO1 = MI1->getOperand(1);
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if (Opcode == ARM::LDRi12 && (!MO0.isCPI() || !MO1.isCPI()))
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return false;
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if (MO0.getOffset() != MO1.getOffset())
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return false;
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@ -14,7 +14,11 @@ define void @t(i32* nocapture %vals, i32 %c) nounwind {
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entry:
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; ARM: t:
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; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
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; ARM-NOT: ldr r{{[0-9]+}}, LCPI0_1
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; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
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; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
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; to add the pseudo instructions to make sure they are CSE'ed at the same
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; time as the "ldr cp".
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; ARM: ldr r{{[0-9]+}}, LCPI0_1
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; ARM: LPC0_0:
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; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
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; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
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@ -32,7 +36,7 @@ entry:
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bb.nph: ; preds = %entry
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; ARM: LCPI0_0:
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; ARM-NOT: LCPI0_1:
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; ARM: LCPI0_1:
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; ARM: .section
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; THUMB: BB#1
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