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Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative

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value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-01-20 23:55:07 +00:00
parent e906921480
commit d7e3cc840b
2 changed files with 7 additions and 7 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1055,8 +1055,7 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const {
int Opcode = MI0->getOpcode();
if (Opcode == ARM::LDRi12 ||
Opcode == ARM::t2LDRpci ||
if (Opcode == ARM::t2LDRpci ||
Opcode == ARM::t2LDRpci_pic ||
Opcode == ARM::tLDRpci ||
Opcode == ARM::tLDRpci_pic ||
@ -1069,9 +1068,6 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
const MachineOperand &MO0 = MI0->getOperand(1);
const MachineOperand &MO1 = MI1->getOperand(1);
if (Opcode == ARM::LDRi12 && (!MO0.isCPI() || !MO1.isCPI()))
return false;
if (MO0.getOffset() != MO1.getOffset())
return false;

8
test/CodeGen/ARM/machine-licm.ll
View File

@ -14,7 +14,11 @@ define void @t(i32* nocapture %vals, i32 %c) nounwind {
entry:
; ARM: t:
; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
; ARM-NOT: ldr r{{[0-9]+}}, LCPI0_1
; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
; to add the pseudo instructions to make sure they are CSE'ed at the same
; time as the "ldr cp".
; ARM: ldr r{{[0-9]+}}, LCPI0_1
; ARM: LPC0_0:
; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
@ -32,7 +36,7 @@ entry:
bb.nph: ; preds = %entry
; ARM: LCPI0_0:
; ARM-NOT: LCPI0_1:
; ARM: LCPI0_1:
; ARM: .section
; THUMB: BB#1